otsdaq_prepmodernization  v2_05_02_indev
ethernet_controller.vhd
1 -------------------------------------------------------------------------------
2 --
3 -- Title : DIG Gigabit Ethernet Controller
4 -- Design : ethernet_controller
5 -- Author : Ryan Rivera
6 -- Company : FNAL
7 --
8 -------------------------------------------------------------------------------
9 --
10 -- File : d:\Projects\otsdaq\OtS Ethernet MAC firmware\ActiveHDL_proj\ethernet_controller\compile\ethernet_controller.vhd
11 -- Generated : Mon Feb 29 11:09:28 2016
12 -- From : d:/Projects/otsdaq/OtS Ethernet MAC firmware/ActiveHDL_proj/ethernet_controller/src/ethernet_controller.bde
13 -- By : Bde2Vhdl ver. 2.6
14 --
15 -------------------------------------------------------------------------------
16 --
17 -- Description :
18 --
19 -------------------------------------------------------------------------------
20 -- Design unit header --
21 library IEEE;
22 use IEEE.std_logic_1164.all;
23 
24 
25 entity ethernet_controller is
26  port(
27  GMII_RX_CLK : in STD_LOGIC;
28  GMII_RX_DV : in STD_LOGIC;
29  GMII_RX_ER : in STD_LOGIC;
30  arp_announce : in STD_LOGIC;
31  reset : in STD_LOGIC;
32  trigger : in STD_LOGIC;
33  GMII_RXD : in STD_LOGIC_VECTOR(7 downto 0);
34  dest_addr : in STD_LOGIC_VECTOR(31 downto 0);
35  dest_mac : in STD_LOGIC_VECTOR(47 downto 0);
36  dest_port : in STD_LOGIC_VECTOR(15 downto 0);
37  self_addr : in STD_LOGIC_VECTOR(31 downto 0);
38  self_mac : in STD_LOGIC_VECTOR(47 downto 0);
39  self_port : in STD_LOGIC_VECTOR(15 downto 0);
40  user_tx_data_in : in std_logic_vector(7 downto 0);
41  user_tx_size_in : in STD_LOGIC_VECTOR(10 downto 0);
42  GMII_GTX_CLK : out STD_LOGIC;
43  GMII_TX_EN : out STD_LOGIC;
44  GMII_TX_ER : out STD_LOGIC;
45  busy : out STD_LOGIC;
46  crc_chk_en : out STD_LOGIC;
47  crc_chk_init : out STD_LOGIC;
48  crc_chk_rd : out STD_LOGIC;
49  crc_gen_en : out std_logic;
50  crc_gen_init : out std_logic;
51  crc_gen_rd : out std_logic;
52  en_tx_data : out STD_LOGIC;
53  four_bit_mode_out : out STD_LOGIC;
54  src_capture_for_ctrl : out STD_LOGIC;
55  src_capture_for_data : out STD_LOGIC;
56  user_rx_valid_out : out STD_LOGIC;
57  GMII_TXD : out STD_LOGIC_VECTOR(7 downto 0);
58  crc_chk_din : out STD_LOGIC_VECTOR(7 downto 0);
59  src_addr : out STD_LOGIC_VECTOR(31 downto 0);
60  src_mac : out STD_LOGIC_VECTOR(47 downto 0);
61  src_port : out STD_LOGIC_VECTOR(15 downto 0);
62  udp_data_count : out STD_LOGIC_VECTOR(10 downto 0);
63  udp_dest_port : out STD_LOGIC_VECTOR(15 downto 0);
64  user_rx_data_out : out STD_LOGIC_VECTOR(7 downto 0)
65  );
66 end ethernet_controller;
67 
68 architecture arch of ethernet_controller is
69 
70 ---- Component declarations -----
71 
72 component address_container
73  port (
74  capture : in STD_LOGIC;
75  clk : in STD_LOGIC;
76  data_in : in STD_LOGIC_VECTOR(7 downto 0);
77  protocol_ping_strobe : out STD_LOGIC;
78  set_ctrl_dest_strobe : out STD_LOGIC;
79  set_data_dest_strobe : out STD_LOGIC
80  );
81 end component;
82 component icmp_ping_checksum_calc
83  port (
84  clk : in STD_LOGIC;
85  req_chk_sum : in STD_LOGIC_VECTOR(15 downto 0);
86  reset : in STD_LOGIC;
87  trigger : in STD_LOGIC;
88  resp_chk_sum : out STD_LOGIC_VECTOR(15 downto 0)
89  );
90 end component;
91 component icmp_ping_shift_reg
92  port (
93  clk : in STD_LOGIC;
94  din : in STD_LOGIC_VECTOR(7 downto 0);
95  ds_clken : in STD_LOGIC;
96  us_clken : in STD_LOGIC;
97  dout : out STD_LOGIC_VECTOR(7 downto 0)
98  );
99 end component;
100 component ip_checksum_calc
101  port (
102  clk : in STD_LOGIC;
103  dest_in : in STD_LOGIC_VECTOR(31 downto 0);
104  icmp_mode : in STD_LOGIC;
105  length_in : in STD_LOGIC_VECTOR(10 downto 0);
106  reset : in STD_LOGIC;
107  src_in : in STD_LOGIC_VECTOR(31 downto 0);
108  trigger : in STD_LOGIC;
109  cs : out STD_LOGIC_VECTOR(15 downto 0)
110  );
111 end component;
112 component user_addrs_mux
113  port (
114  icmp_dest_addr : in STD_LOGIC_VECTOR(31 downto 0);
115  icmp_length : in STD_LOGIC_VECTOR(10 downto 0);
116  icmp_mode : in STD_LOGIC;
117  ping_mode : in STD_LOGIC;
118  user_dest_addr : in STD_LOGIC_VECTOR(31 downto 0);
119  user_length : in STD_LOGIC_VECTOR(10 downto 0);
120  ip_dest_addr : out STD_LOGIC_VECTOR(31 downto 0);
121  ip_tx_length : out STD_LOGIC_VECTOR(10 downto 0)
122  );
123 end component;
124 component arp_reply
125  port (
126  addrs : in STD_LOGIC_VECTOR(31 downto 0);
127  arp_announce : in STD_LOGIC;
128  clk : in STD_LOGIC;
129  four_bit_mode : in STD_LOGIC;
130  mac : in STD_LOGIC_VECTOR(47 downto 0);
131  reset : in STD_LOGIC;
132  tip : in STD_LOGIC_VECTOR(31 downto 0);
133  tmac : in STD_LOGIC_VECTOR(47 downto 0);
134  trigger : in STD_LOGIC;
135  udp_busy : in STD_LOGIC;
136  arp_busy : out STD_LOGIC;
137  crc_gen_en : out STD_LOGIC;
138  crc_gen_init : out STD_LOGIC;
139  crc_gen_rd : out STD_LOGIC;
140  dataout : out STD_LOGIC_VECTOR(7 downto 0);
141  tx_en : out STD_LOGIC;
142  tx_er : out STD_LOGIC
143  );
144 end component;
145 component create_packet
146  port (
147  addrs : in STD_LOGIC_VECTOR(31 downto 0);
148  arp_busy : in STD_LOGIC;
149  checksum : in STD_LOGIC_VECTOR(15 downto 0);
150  clk : in STD_LOGIC;
151  data_length : in STD_LOGIC_VECTOR(10 downto 0);
152  dest_ip : in STD_LOGIC_VECTOR(31 downto 0);
153  dest_mac : in STD_LOGIC_VECTOR(47 downto 0);
154  dest_port : in STD_LOGIC_VECTOR(15 downto 0);
155  four_bit_mode : in STD_LOGIC;
156  icmp_checksum : in STD_LOGIC_VECTOR(15 downto 0);
157  icmp_data : in STD_LOGIC_VECTOR(7 downto 0);
158  icmp_ip : in STD_LOGIC_VECTOR(31 downto 0);
159  icmp_mac : in STD_LOGIC_VECTOR(47 downto 0);
160  icmp_ping : in STD_LOGIC;
161  mac : in STD_LOGIC_VECTOR(47 downto 0);
162  ping : in STD_LOGIC;
163  reset : in STD_LOGIC;
164  trigger : in STD_LOGIC;
165  busy : out STD_LOGIC;
166  checksum_trig : out STD_LOGIC := '0';
167  clken_out : out STD_LOGIC;
168  crc_gen_en : out STD_LOGIC;
169  crc_gen_init : out STD_LOGIC;
170  crc_gen_rd : out STD_LOGIC;
171  dataout : out STD_LOGIC_VECTOR(7 downto 0);
172  en_tx_data : out STD_LOGIC;
173  length_count_out : out STD_LOGIC_VECTOR(10 downto 0);
174  tx_en : out STD_LOGIC;
175  tx_er : out STD_LOGIC;
176  tx_icmp_packet : out STD_LOGIC;
177  udp_data_sel : out STD_LOGIC
178  );
179 end component;
180 component dataout_mux
181  port (
182  arp_data_out : in STD_LOGIC_VECTOR(7 downto 0);
183  arp_tx_en : in STD_LOGIC;
184  arp_tx_er : in STD_LOGIC;
185  sel_udp : in STD_LOGIC;
186  udp_data_out : in STD_LOGIC_VECTOR(7 downto 0);
187  udp_tx_en : in STD_LOGIC;
188  udp_tx_er : in STD_LOGIC;
189  tx_en : out STD_LOGIC;
190  tx_er : out STD_LOGIC;
191  txd : out STD_LOGIC_VECTOR(7 downto 0)
192  );
193 end component;
194 component decipherer
195  port (
196  clk : in STD_LOGIC;
197  data_in : in STD_LOGIC_VECTOR(7 downto 0);
198  dv : in STD_LOGIC;
199  er : in STD_LOGIC;
200  reset : in STD_LOGIC;
201  self_addrs : in STD_LOGIC_VECTOR(31 downto 0);
202  arp_req_ip : out STD_LOGIC_VECTOR(31 downto 0);
203  arp_req_mac : out STD_LOGIC_VECTOR(47 downto 0);
204  arp_search_ip : out STD_LOGIC_VECTOR(31 downto 0);
205  capture_source_addrs : out STD_LOGIC;
206  clken_out : out STD_LOGIC;
207  crc_chk_en : out STD_LOGIC;
208  crc_chk_init : out STD_LOGIC;
209  crc_chk_rd : out STD_LOGIC;
210  data_out : out STD_LOGIC_VECTOR(7 downto 0);
211  dest_mac : out STD_LOGIC_VECTOR(47 downto 0);
212  four_bit_mode_out : out STD_LOGIC;
213  icmp_checksum : out STD_LOGIC_VECTOR(15 downto 0);
214  ip_data_count : out STD_LOGIC_VECTOR(10 downto 0);
215  is_arp : out STD_LOGIC;
216  is_icmp_ping : out STD_LOGIC;
217  is_idle : out STD_LOGIC;
218  is_ip : out STD_LOGIC;
219  is_udp : out STD_LOGIC;
220  src_mac : out STD_LOGIC_VECTOR(47 downto 0);
221  udp_data_count : out STD_LOGIC_VECTOR(10 downto 0);
222  udp_data_valid : out STD_LOGIC;
223  udp_dest_port_out : out STD_LOGIC_VECTOR(15 downto 0);
224  udp_src_ip : out STD_LOGIC_VECTOR(31 downto 0);
225  udp_src_port : out STD_LOGIC_VECTOR(15 downto 0)
226  );
227 end component;
228 component filter_data_out
229  port (
230  clk : in STD_LOGIC;
231  enable : in STD_LOGIC;
232  rx_data : in STD_LOGIC_VECTOR(7 downto 0);
233  us_clken : in STD_LOGIC;
234  out_data : out STD_LOGIC_VECTOR(7 downto 0);
235  out_data_valid : out STD_LOGIC
236  );
237 end component;
238 component or33
239  port (
240  a1 : in std_logic;
241  a2 : in std_logic;
242  b1 : in std_logic;
243  b2 : in std_logic;
244  c1 : in std_logic;
245  c2 : in std_logic;
246  ao : out std_logic;
247  bo : out std_logic;
248  co : out std_logic
249  );
250 end component;
251 component udp_data_splicer
252  port (
253  clk : in std_logic;
254  gen_data : in std_logic_vector(7 downto 0);
255  sel_user : in std_logic;
256  user_data : in std_logic_vector(7 downto 0);
257  udp_data_out : out std_logic_vector(7 downto 0)
258  );
259 end component;
260 
261 ---- Signal declarations used on the diagram ----
262 
263 signal arp_announce_strobe : STD_LOGIC;
264 signal arp_busy : STD_LOGIC;
265 signal arp_crc_gen_en_sig : STD_LOGIC;
266 signal arp_crc_gen_init_sig : STD_LOGIC;
267 signal arp_crc_gen_rd_sig : STD_LOGIC;
268 signal arp_trigger : STD_LOGIC;
269 signal arp_tx_en : STD_LOGIC;
270 signal arp_tx_er : STD_LOGIC;
271 signal busy_sig : STD_LOGIC;
272 signal capture_addrs : STD_LOGIC;
273 signal checksum_trig : STD_LOGIC;
274 signal clk : STD_LOGIC;
275 signal crc_chk_en_sig : STD_LOGIC;
276 signal crc_chk_init_sig : STD_LOGIC;
277 signal crc_chk_rd_sig : STD_LOGIC;
278 signal crc_gen_en_sig : std_logic;
279 signal crc_gen_init_sig : std_logic;
280 signal crc_gen_rd_sig : std_logic;
281 signal create_clken : STD_LOGIC;
282 signal decipher_clken : STD_LOGIC;
283 signal dec_chk_rd_sig : STD_LOGIC;
284 signal en_tx_data_sig : STD_LOGIC;
285 signal four_bit_mode : STD_LOGIC;
286 signal is_arp_packet_sig : STD_LOGIC;
287 signal is_icmp_packet_sig : STD_LOGIC;
288 signal is_ip_packet_sig : STD_LOGIC;
289 signal oei_protocol_ping_strobe : STD_LOGIC;
290 signal rx_dv : STD_LOGIC;
291 signal rx_er : STD_LOGIC;
292 signal sel_udp : STD_LOGIC;
293 signal set_ctrl_dest_strobe : STD_LOGIC;
294 signal set_data_dest_strobe : STD_LOGIC;
295 signal trigger_sig : STD_LOGIC;
296 signal tx_en : STD_LOGIC;
297 signal tx_er : STD_LOGIC;
298 signal tx_icmp_packet : STD_LOGIC;
299 signal udp_crc_gen_en_sig : std_logic;
300 signal udp_crc_gen_init_sig : std_logic;
301 signal udp_crc_gen_rd_sig : std_logic;
302 signal udp_data_valid : STD_LOGIC;
303 signal udp_tx_en : STD_LOGIC;
304 signal udp_tx_er : STD_LOGIC;
305 signal arp_data_out : STD_LOGIC_VECTOR(7 downto 0);
306 signal arp_req_ip : STD_LOGIC_VECTOR(31 downto 0);
307 signal arp_req_mac : STD_LOGIC_VECTOR(47 downto 0);
308 signal checksum : STD_LOGIC_VECTOR(15 downto 0);
309 signal data_out : STD_LOGIC_VECTOR(7 downto 0);
310 signal decipher_dout : STD_LOGIC_VECTOR(7 downto 0);
311 signal frame_src_mac : STD_LOGIC_VECTOR(47 downto 0);
312 signal icmp_checksum : STD_LOGIC_VECTOR(15 downto 0);
313 signal icmp_req_checksum : STD_LOGIC_VECTOR(15 downto 0);
314 signal ip_data_count_sig : STD_LOGIC_VECTOR(10 downto 0);
315 signal ip_dest_addr : STD_LOGIC_VECTOR(31 downto 0);
316 signal ping_data_delayed : STD_LOGIC_VECTOR(7 downto 0);
317 signal rxd : STD_LOGIC_VECTOR(7 downto 0);
318 signal udp_data_count_sig : STD_LOGIC_VECTOR(10 downto 0);
319 signal udp_data_out : STD_LOGIC_VECTOR(7 downto 0);
320 signal udp_gen_data : STD_LOGIC_VECTOR(7 downto 0);
321 signal udp_src_ip : STD_LOGIC_VECTOR(31 downto 0);
322 signal udp_src_port : STD_LOGIC_VECTOR(15 downto 0);
323 signal udp_tx_length : STD_LOGIC_VECTOR(10 downto 0);
324 signal user_tx_size_in_latched : STD_LOGIC_VECTOR(10 downto 0);
325 
326 begin
327 
328 ---- Component instantiations ----
329 
330 AddressContainer : address_container
331  port map(
332  capture => capture_addrs,
333  clk => clk,
334  data_in => decipher_dout,
335  protocol_ping_strobe => oei_protocol_ping_strobe,
336  set_ctrl_dest_strobe => set_ctrl_dest_strobe,
337  set_data_dest_strobe => set_data_dest_strobe
338  );
339 
340 ArpReplyBlock : arp_reply
341  port map(
342  addrs => self_addr,
343  arp_announce => arp_announce_strobe ,
344  arp_busy => arp_busy,
345  clk => clk,
346  crc_gen_en => arp_crc_gen_en_sig ,
347  crc_gen_init => arp_crc_gen_init_sig ,
348  crc_gen_rd => arp_crc_gen_rd_sig ,
349  dataout => arp_data_out ,
350  four_bit_mode => four_bit_mode,
351  mac => self_mac,
352  reset => reset,
353  tip => arp_req_ip,
354  tmac => arp_req_mac,
355  trigger => arp_trigger,
356  tx_en => arp_tx_en,
357  tx_er => arp_tx_er,
358  udp_busy => sel_udp
359  );
360 
361 CRC_OR : or33
362  port map(
363  a1 => arp_crc_gen_en_sig,
364  a2 => udp_crc_gen_en_sig,
365  ao => crc_gen_en_sig,
366  b1 => arp_crc_gen_init_sig,
367  b2 => udp_crc_gen_init_sig,
368  bo => crc_gen_init_sig ,
369  c1 => arp_crc_gen_rd_sig,
370  c2 => udp_crc_gen_rd_sig,
371  co => crc_gen_rd_sig
372  );
373 
374 ChecksumCalcBlock : ip_checksum_calc
375  port map(
376  clk => clk,
377  cs => checksum,
378  dest_in => ip_dest_addr ,
379  icmp_mode => tx_icmp_packet ,
380  length_in => user_tx_size_in_latched,
381  reset => reset,
382  src_in => self_addr,
383  trigger => checksum_trig
384  );
385 
386 CreatePacketBlock : create_packet
387  port map(
388  addrs => self_addr,
389  arp_busy => arp_busy,
390  busy => busy_sig,
391  checksum => checksum,
392  checksum_trig => checksum_trig,
393  clk => clk,
394  clken_out => create_clken,
395  crc_gen_en => udp_crc_gen_en_sig ,
396  crc_gen_init => udp_crc_gen_init_sig ,
397  crc_gen_rd => udp_crc_gen_rd_sig ,
398  data_length => udp_tx_length,
399  dataout => udp_gen_data ,
400  dest_ip => dest_addr,
401  dest_mac => dest_mac,
402  dest_port => dest_port,
403  en_tx_data => en_tx_data_sig,
404  four_bit_mode => four_bit_mode,
405  icmp_checksum => icmp_checksum,
406  icmp_data => ping_data_delayed ,
407  icmp_ip => udp_src_ip,
408  icmp_mac => frame_src_mac ,
409  icmp_ping => is_icmp_packet_sig ,
410  length_count_out => user_tx_size_in_latched ,
411  mac => self_mac,
412  ping => oei_protocol_ping_strobe ,
413  reset => reset,
414  trigger => trigger_sig,
415  tx_en => udp_tx_en,
416  tx_er => udp_tx_er,
417  tx_icmp_packet => tx_icmp_packet,
418  udp_data_sel => sel_udp
419  );
420 
421 DataoutMux : dataout_mux
422  port map(
423  arp_data_out => arp_data_out,
424  arp_tx_en => arp_tx_en,
425  arp_tx_er => arp_tx_er,
426  sel_udp => sel_udp,
427  tx_en => tx_en,
428  tx_er => tx_er,
429  txd => data_out,
430  udp_data_out => udp_data_out,
431  udp_tx_en => udp_tx_en,
432  udp_tx_er => udp_tx_er
433  );
434 
435 DecipherBlock : decipherer
436  port map(
437  arp_req_ip => arp_req_ip,
438  arp_req_mac => arp_req_mac,
439  capture_source_addrs => capture_addrs ,
440  clk => clk,
441  clken_out => decipher_clken ,
442  crc_chk_en => crc_chk_en_sig,
443  crc_chk_init => crc_chk_init_sig,
444  crc_chk_rd => dec_chk_rd_sig,
445  data_in => rxd,
446  data_out => decipher_dout ,
447  dv => rx_dv,
448  er => rx_er,
449  four_bit_mode_out => four_bit_mode ,
450  icmp_checksum => icmp_req_checksum,
451  ip_data_count => ip_data_count_sig,
452  is_arp => is_arp_packet_sig ,
453  is_icmp_ping => is_icmp_packet_sig,
454  is_ip => is_ip_packet_sig ,
455  reset => reset,
456  self_addrs => self_addr,
457  src_mac => frame_src_mac,
458  udp_data_count => udp_data_count_sig,
459  udp_data_valid => udp_data_valid,
460  udp_dest_port_out => udp_dest_port ,
461  udp_src_ip => udp_src_ip,
462  udp_src_port => udp_src_port
463  );
464 
465 FilterDataOutBlock : filter_data_out
466  port map(
467  clk => clk,
468  enable => udp_data_valid ,
469  out_data => user_rx_data_out ,
470  out_data_valid => user_rx_valid_out,
471  rx_data => decipher_dout,
472  us_clken => decipher_clken
473  );
474 
475 ICMPPingChecksumCalcBlock : icmp_ping_checksum_calc
476  port map(
477  clk => clk,
478  req_chk_sum => icmp_req_checksum,
479  reset => reset,
480  resp_chk_sum => icmp_checksum,
481  trigger => trigger_sig
482  );
483 
484 ICMPPingShiftRegBlock : icmp_ping_shift_reg
485  port map(
486  clk => clk,
487  din => decipher_dout,
488  dout => ping_data_delayed ,
489  ds_clken => create_clken,
490  us_clken => decipher_clken
491  );
492 
493 trigger_sig <= trigger or oei_protocol_ping_strobe or is_icmp_packet_sig;
494 
495 crc_chk_rd_sig <= is_ip_packet_sig and dec_chk_rd_sig;
496 
497 arp_trigger <= arp_announce_strobe or is_arp_packet_sig;
498 
499 UDPDataSplicer : udp_data_splicer
500  port map(
501  clk => clk,
502  gen_data => udp_gen_data,
503  sel_user => en_tx_data_sig,
504  udp_data_out => udp_data_out,
505  user_data => user_tx_data_in
506  );
507 
508 UdpLengthMux : user_addrs_mux
509  port map(
510  icmp_dest_addr => udp_src_ip,
511  icmp_length => ip_data_count_sig,
512  icmp_mode => tx_icmp_packet ,
513  ip_dest_addr => ip_dest_addr,
514  ip_tx_length => udp_tx_length,
515  ping_mode => capture_addrs,
516  user_dest_addr => dest_addr,
517  user_length => user_tx_size_in
518  );
519 
520 
521 ---- Terminal assignment ----
522 
523  -- Inputs terminals
524  rxd <= GMII_RXD;
525  clk <= GMII_RX_CLK;
526  rx_dv <= GMII_RX_DV;
527  rx_er <= GMII_RX_ER;
528  arp_announce_strobe <= arp_announce;
529 
530  -- Output\buffer terminals
531  GMII_GTX_CLK <= clk;
532  GMII_TXD <= data_out;
533  GMII_TX_EN <= tx_en;
534  GMII_TX_ER <= tx_er;
535  busy <= busy_sig;
536  crc_chk_din <= decipher_dout;
537  crc_chk_en <= crc_chk_en_sig;
538  crc_chk_init <= crc_chk_init_sig;
539  crc_chk_rd <= crc_chk_rd_sig;
540  crc_gen_en <= crc_gen_en_sig;
541  crc_gen_init <= crc_gen_init_sig;
542  crc_gen_rd <= crc_gen_rd_sig;
543  en_tx_data <= en_tx_data_sig;
544  four_bit_mode_out <= four_bit_mode;
545  src_addr <= udp_src_ip;
546  src_capture_for_ctrl <= set_ctrl_dest_strobe;
547  src_capture_for_data <= set_data_dest_strobe;
548  src_mac <= frame_src_mac;
549  src_port <= udp_src_port;
550  udp_data_count <= udp_data_count_sig;
551 
552 
553 end arch;
udp_data_splicer
Definition: udp_data_splicer.vhd:8
arp_reply
Definition: arp_reply.vhd:26
dataout_mux
Definition: dataout_mux.vhd:8
icmp_ping_checksum_calc
Definition: icmp_ping_checksum_calc.vhd:25
ip_checksum_calc
Definition: ip_checksum_calc.vhd:26
address_container
Definition: address_container.vhd:21
create_packet
Definition: create_packet.vhd:26
or33
Definition: or33.vhd:8
ethernet_controller
Definition: ethernet_controller.vhd:25
user_addrs_mux
Definition: user_addrs_mux.vhd:8
filter_data_out
Definition: filter_data_out.vhd:9
icmp_ping_shift_reg
Definition: icmp_ping_shift_reg.vhd:6