otsdaq_prepmodernization  v2_05_02_indev
DIG_GEC.vhd
1 -------------------------------------------------------------------------------
2 --
3 -- Title : DIG Gigabit Ethernet Controller
4 -- Design : ethernet_controller
5 -- Author : Ryan Rivera
6 -- Company : FNAL
7 --
8 -------------------------------------------------------------------------------
9 --
10 -- File : c:\HDL_Designs\dig_gec\ethernet_controller\compile\DIG_GEC.vhd
11 -- Generated : Fri Mar 20 15:19:34 2009
12 -- From : c:/HDL_Designs/dig_gec/ethernet_controller/src/DIG_GEC.bde
13 -- By : Bde2Vhdl ver. 2.6
14 --
15 -------------------------------------------------------------------------------
16 --
17 -- Description :
18 --
19 -------------------------------------------------------------------------------
20 -- Design unit header --
21 library IEEE;
22 use IEEE.std_logic_1164.all;
23 
24 
25 entity DIG_GEC is
26  port(
27  GMII_RX_CLK : in STD_LOGIC;
28  GMII_RX_DV : in STD_LOGIC;
29  GMII_RX_ER : in STD_LOGIC;
30  reset : in STD_LOGIC;
31  test_mode : in STD_LOGIC;
32  trigger : in STD_LOGIC;
33  GMII_RXD : in std_logic_vector(7 downto 0);
34  user_addrs : in STD_LOGIC_VECTOR(7 downto 0);
35  user_tx_data_in : in std_logic_vector(7 downto 0);
36  user_tx_size_in : in STD_LOGIC_VECTOR(10 downto 0);
37  GMII_GTX_CLK : out STD_LOGIC;
38  GMII_TX_EN : out STD_LOGIC;
39  GMII_TX_ER : out STD_LOGIC;
40  busy : out STD_LOGIC;
41  crc_chk_en : out STD_LOGIC;
42  crc_chk_err : out STD_LOGIC;
43  crc_chk_init : out STD_LOGIC;
44  crc_gen_en : out std_logic;
45  crc_gen_init : out std_logic;
46  crc_gen_rd : out std_logic;
47  en_tx_data : out std_logic;
48  udp_data_valid_out : out std_logic;
49  GMII_TXD : out STD_LOGIC_VECTOR(7 downto 0);
50  udp_data_count : out STD_LOGIC_VECTOR(10 downto 0);
51  user_rx_data_out : out std_logic_vector(7 downto 0)
52  );
53 end DIG_GEC;
54 
55 architecture DIG_GEC of DIG_GEC is
56 
57 ---- Component declarations -----
58 
59 component arp_reply
60  port (
61  addrs : in STD_LOGIC_VECTOR(7 downto 0);
62  clk : in STD_LOGIC;
63  reset : in STD_LOGIC;
64  tip : in STD_LOGIC_VECTOR(31 downto 0);
65  tmac : in STD_LOGIC_VECTOR(47 downto 0);
66  trigger : in STD_LOGIC;
67  udp_busy : in STD_LOGIC;
68  arp_busy : out STD_LOGIC;
69  crc_gen_en : out STD_LOGIC;
70  crc_gen_init : out STD_LOGIC;
71  crc_gen_rd : out STD_LOGIC;
72  dataout : out STD_LOGIC_VECTOR(7 downto 0);
73  tx_en : out STD_LOGIC;
74  tx_er : out STD_LOGIC
75  );
76 end component;
77 component create_packet
78  port (
79  addrs : in STD_LOGIC_VECTOR(7 downto 0);
80  arp_busy : in STD_LOGIC;
81  checksum : in STD_LOGIC_VECTOR(15 downto 0);
82  clk : in STD_LOGIC;
83  data_length : in STD_LOGIC_VECTOR(10 downto 0);
84  dest_ip : in STD_LOGIC_VECTOR(31 downto 0);
85  dest_mac : in STD_LOGIC_VECTOR(47 downto 0);
86  dest_port : in STD_LOGIC_VECTOR(15 downto 0);
87  ping : in STD_LOGIC;
88  reset : in STD_LOGIC;
89  trigger : in STD_LOGIC;
90  busy : out STD_LOGIC;
91  crc_gen_en : out STD_LOGIC;
92  crc_gen_init : out STD_LOGIC;
93  crc_gen_rd : out STD_LOGIC;
94  dataout : out STD_LOGIC_VECTOR(7 downto 0);
95  en_tx_data : out STD_LOGIC;
96  tx_en : out STD_LOGIC;
97  tx_er : out STD_LOGIC;
98  udp_data_sel : out STD_LOGIC
99  );
100 end component;
101 component dataout_mux
102  port (
103  arp_data_out : in STD_LOGIC_VECTOR(7 downto 0);
104  arp_tx_en : in STD_LOGIC;
105  arp_tx_er : in STD_LOGIC;
106  sel_udp : in STD_LOGIC;
107  udp_data_out : in STD_LOGIC_VECTOR(7 downto 0);
108  udp_tx_en : in STD_LOGIC;
109  udp_tx_er : in STD_LOGIC;
110  tx_en : out STD_LOGIC;
111  tx_er : out STD_LOGIC;
112  txd : out STD_LOGIC_VECTOR(7 downto 0)
113  );
114 end component;
115 component decipherer
116  port (
117  addrs : in STD_LOGIC_VECTOR(7 downto 0);
118  clk : in STD_LOGIC;
119  data : in STD_LOGIC_VECTOR(7 downto 0);
120  dv : in STD_LOGIC;
121  er : in STD_LOGIC;
122  reset : in STD_LOGIC;
123  arp_req_ip : out STD_LOGIC_VECTOR(31 downto 0);
124  arp_req_mac : out STD_LOGIC_VECTOR(47 downto 0);
125  arp_search_ip : out STD_LOGIC_VECTOR(31 downto 0);
126  capture_source_addrs : out STD_LOGIC;
127  crc_chk_en : out STD_LOGIC;
128  crc_chk_err : out STD_LOGIC;
129  crc_chk_init : out STD_LOGIC;
130  dest_mac : out STD_LOGIC_VECTOR(47 downto 0);
131  is_arp : out STD_LOGIC;
132  is_idle : out STD_LOGIC;
133  is_udp : out STD_LOGIC;
134  src_mac : out STD_LOGIC_VECTOR(47 downto 0);
135  udp_data_count : out STD_LOGIC_VECTOR(10 downto 0);
136  udp_data_valid : out STD_LOGIC;
137  udp_dest_ip_out : out STD_LOGIC_VECTOR(31 downto 0);
138  udp_src_ip : out STD_LOGIC_VECTOR(31 downto 0);
139  udp_src_port : out STD_LOGIC_VECTOR(15 downto 0)
140  );
141 end component;
142 component dest_info_container
143  port (
144  clk : in STD_LOGIC;
145  ip_from_udp : in STD_LOGIC_VECTOR(31 downto 0);
146  mac_from_udp : in STD_LOGIC_VECTOR(47 downto 0);
147  port_from_udp : in STD_LOGIC_VECTOR(15 downto 0);
148  reset : in STD_LOGIC;
149  we : in STD_LOGIC;
150  dest_ip : out STD_LOGIC_VECTOR(31 downto 0);
151  dest_mac : out STD_LOGIC_VECTOR(47 downto 0);
152  dest_port : out STD_LOGIC_VECTOR(15 downto 0)
153  );
154 end component;
155 component filter_data_out
156  port (
157  enable : in std_logic;
158  rx_data : in std_logic_vector(7 downto 0);
159  out_data : out std_logic_vector(7 downto 0)
160  );
161 end component;
162 component ip_checksum_calc
163  port (
164  addrs : in std_logic_vector(7 downto 0);
165  clk : in std_logic;
166  length : in std_logic_vector(10 downto 0);
167  reset : in std_logic;
168  trigger : in std_logic;
169  cs : out std_logic_vector(15 downto 0)
170  );
171 end component;
172 component or33
173  port (
174  a1 : in std_logic;
175  a2 : in std_logic;
176  b1 : in std_logic;
177  b2 : in std_logic;
178  c1 : in std_logic;
179  c2 : in std_logic;
180  ao : out std_logic;
181  bo : out std_logic;
182  co : out std_logic
183  );
184 end component;
185 component udp_data_splicer
186  port (
187  clk : in std_logic;
188  gen_data : in std_logic_vector(7 downto 0);
189  sel_user : in std_logic;
190  user_data : in std_logic_vector(7 downto 0);
191  udp_data_out : out std_logic_vector(7 downto 0)
192  );
193 end component;
194 component user_addrs_mux
195  port (
196  ping_mode : in STD_LOGIC;
197  test_mode : in STD_LOGIC;
198  user_addrs : in STD_LOGIC_VECTOR(7 downto 0);
199  user_length : in STD_LOGIC_VECTOR(10 downto 0);
200  addrs_out : out STD_LOGIC_VECTOR(7 downto 0);
201  udp_tx_length : out STD_LOGIC_VECTOR(10 downto 0)
202  );
203 end component;
204 
205 ---- Signal declarations used on the diagram ----
206 
207 signal arp_busy : STD_LOGIC;
208 signal arp_crc_gen_en_sig : STD_LOGIC;
209 signal arp_crc_gen_init_sig : STD_LOGIC;
210 signal arp_crc_gen_rd_sig : STD_LOGIC;
211 signal arp_tx_en : STD_LOGIC;
212 signal arp_tx_er : STD_LOGIC;
213 signal busy_sig : STD_LOGIC;
214 signal capture_addrs : STD_LOGIC;
215 signal clk : STD_LOGIC;
216 signal crc_chk_en_sig : STD_LOGIC;
217 signal crc_chk_err_sig : STD_LOGIC;
218 signal crc_chk_init_sig : STD_LOGIC;
219 signal crc_gen_en_sig : std_logic;
220 signal crc_gen_init_sig : std_logic;
221 signal crc_gen_rd_sig : std_logic;
222 signal dec_chk_err_sig : STD_LOGIC;
223 signal en_tx_data_sig : STD_LOGIC;
224 signal is_arp_packet_sig : STD_LOGIC;
225 signal is_idle : STD_LOGIC;
226 signal is_udp_packet_sig : STD_LOGIC;
227 signal sel_udp : STD_LOGIC;
228 signal trigger_sig : STD_LOGIC;
229 signal tx_en : STD_LOGIC;
230 signal tx_er : STD_LOGIC;
231 signal udp_crc_gen_en_sig : std_logic;
232 signal udp_crc_gen_init_sig : std_logic;
233 signal udp_crc_gen_rd_sig : std_logic;
234 signal udp_datasplicer_sel : std_logic;
235 signal udp_data_valid : std_logic;
236 signal udp_tx_en : STD_LOGIC;
237 signal udp_tx_er : STD_LOGIC;
238 signal addrs_sig : STD_LOGIC_VECTOR (7 downto 0);
239 signal arp_data_out : STD_LOGIC_VECTOR (7 downto 0);
240 signal arp_req_ip : STD_LOGIC_VECTOR (31 downto 0);
241 signal arp_req_mac : STD_LOGIC_VECTOR (47 downto 0);
242 signal arp_search_ip : STD_LOGIC_VECTOR (31 downto 0);
243 signal checksum : STD_LOGIC_VECTOR (15 downto 0);
244 signal data_out : STD_LOGIC_VECTOR (7 downto 0);
245 signal dest_ip : STD_LOGIC_VECTOR (31 downto 0);
246 signal dest_mac : STD_LOGIC_VECTOR (47 downto 0);
247 signal dest_port : STD_LOGIC_VECTOR (15 downto 0);
248 signal frame_dest_mac : STD_LOGIC_VECTOR (47 downto 0);
249 signal frame_src_mac : STD_LOGIC_VECTOR (47 downto 0);
250 signal udp_data_count_sig : STD_LOGIC_VECTOR (10 downto 0);
251 signal udp_data_out : STD_LOGIC_VECTOR (7 downto 0);
252 signal udp_dest_ip : STD_LOGIC_VECTOR (31 downto 0);
253 signal udp_gen_data : STD_LOGIC_VECTOR (7 downto 0);
254 signal udp_src_ip : STD_LOGIC_VECTOR (31 downto 0);
255 signal udp_src_port : STD_LOGIC_VECTOR (15 downto 0);
256 signal udp_tx_length : STD_LOGIC_VECTOR (10 downto 0);
257 
258 begin
259 
260 ---- Component instantiations ----
261 
262 ArpReplyBlock : arp_reply
263  port map(
264  addrs => addrs_sig,
265  arp_busy => arp_busy,
266  clk => clk,
267  crc_gen_en => arp_crc_gen_en_sig ,
268  crc_gen_init => arp_crc_gen_init_sig ,
269  crc_gen_rd => arp_crc_gen_rd_sig ,
270  dataout => arp_data_out ,
271  reset => reset,
272  tip => arp_req_ip,
273  tmac => arp_req_mac,
274  trigger => is_arp_packet_sig ,
275  tx_en => arp_tx_en,
276  tx_er => arp_tx_er,
277  udp_busy => sel_udp
278  );
279 
280 CRC_OR : or33
281  port map(
282  a1 => arp_crc_gen_en_sig,
283  a2 => udp_crc_gen_en_sig,
284  ao => crc_gen_en_sig ,
285  b1 => arp_crc_gen_init_sig,
286  b2 => udp_crc_gen_init_sig,
287  bo => crc_gen_init_sig,
288  c1 => arp_crc_gen_rd_sig,
289  c2 => udp_crc_gen_rd_sig,
290  co => crc_gen_rd_sig
291  );
292 
293 ChecksumCalcBlock : ip_checksum_calc
294  port map(
295  addrs => addrs_sig,
296  clk => clk,
297  cs => checksum,
298  length => udp_tx_length ,
299  reset => reset,
300  trigger => trigger_sig
301  );
302 
303 CreatePacketBlock : create_packet
304  port map(
305  addrs => addrs_sig,
306  arp_busy => arp_busy,
307  busy => busy_sig,
308  checksum => checksum,
309  clk => clk,
310  crc_gen_en => udp_crc_gen_en_sig ,
311  crc_gen_init => udp_crc_gen_init_sig ,
312  crc_gen_rd => udp_crc_gen_rd_sig ,
313  data_length => udp_tx_length,
314  dataout => udp_gen_data ,
315  dest_ip => dest_ip,
316  dest_mac => dest_mac,
317  dest_port => dest_port,
318  en_tx_data => en_tx_data_sig,
319  ping => capture_addrs,
320  reset => reset,
321  trigger => trigger_sig,
322  tx_en => udp_tx_en,
323  tx_er => udp_tx_er,
324  udp_data_sel => sel_udp
325  );
326 
327 DataoutMux : dataout_mux
328  port map(
329  arp_data_out => arp_data_out,
330  arp_tx_en => arp_tx_en,
331  arp_tx_er => arp_tx_er,
332  sel_udp => sel_udp,
333  tx_en => tx_en,
334  tx_er => tx_er,
335  txd => data_out,
336  udp_data_out => udp_data_out,
337  udp_tx_en => udp_tx_en,
338  udp_tx_er => udp_tx_er
339  );
340 
341 DecipherBlock : decipherer
342  port map(
343  addrs => addrs_sig,
344  arp_req_ip => arp_req_ip,
345  arp_req_mac => arp_req_mac,
346  arp_search_ip => arp_search_ip,
347  capture_source_addrs => capture_addrs ,
348  clk => clk,
349  crc_chk_en => crc_chk_en_sig,
350  crc_chk_err => dec_chk_err_sig,
351  crc_chk_init => crc_chk_init_sig,
352  data => GMII_RXD,
353  dest_mac => frame_dest_mac,
354  dv => GMII_RX_DV,
355  er => GMII_RX_ER,
356  is_arp => is_arp_packet_sig ,
357  is_idle => is_idle,
358  is_udp => is_udp_packet_sig ,
359  reset => reset,
360  src_mac => frame_src_mac,
361  udp_data_count => udp_data_count_sig,
362  udp_data_valid => udp_data_valid,
363  udp_dest_ip_out => udp_dest_ip,
364  udp_src_ip => udp_src_ip,
365  udp_src_port => udp_src_port
366  );
367 
368 DestInfoContainer : dest_info_container
369  port map(
370  clk => clk,
371  dest_ip => dest_ip,
372  dest_mac => dest_mac,
373  dest_port => dest_port,
374  ip_from_udp => udp_src_ip,
375  mac_from_udp => frame_src_mac,
376  port_from_udp => udp_src_port,
377  reset => reset,
378  we => capture_addrs
379  );
380 
381 FilterDataOutBlock : filter_data_out
382  port map(
383  enable => udp_data_valid ,
384  out_data => user_rx_data_out ,
385  rx_data => GMII_RXD
386  );
387 
388 udp_datasplicer_sel <= not(test_mode) and en_tx_data_sig;
389 
390 crc_chk_err_sig <= is_udp_packet_sig and dec_chk_err_sig;
391 
392 trigger_sig <= capture_addrs or trigger;
393 
394 UDPDataSplicer : udp_data_splicer
395  port map(
396  clk => clk,
397  gen_data => udp_gen_data,
398  sel_user => udp_datasplicer_sel ,
399  udp_data_out => udp_data_out,
400  user_data => user_tx_data_in
401  );
402 
403 UserAddrsBlock : user_addrs_mux
404  port map(
405  addrs_out => addrs_sig,
406  ping_mode => capture_addrs,
407  test_mode => test_mode,
408  udp_tx_length => udp_tx_length,
409  user_addrs => user_addrs,
410  user_length => user_tx_size_in
411  );
412 
413 
414 ---- Terminal assignment ----
415 
416  -- Inputs terminals
417  clk <= GMII_RX_CLK;
418 
419  -- Output\buffer terminals
420  GMII_GTX_CLK <= clk;
421  GMII_TXD <= data_out;
422  GMII_TX_EN <= tx_en;
423  GMII_TX_ER <= tx_er;
424  busy <= busy_sig;
425  crc_chk_en <= crc_chk_en_sig;
426  crc_chk_err <= crc_chk_err_sig;
427  crc_chk_init <= crc_chk_init_sig;
428  crc_gen_en <= crc_gen_en_sig;
429  crc_gen_init <= crc_gen_init_sig;
430  crc_gen_rd <= crc_gen_rd_sig;
431  en_tx_data <= udp_datasplicer_sel;
432  udp_data_count <= udp_data_count_sig;
433  udp_data_valid_out <= udp_data_valid;
434 
435 
436 end DIG_GEC;
udp_data_splicer
Definition: udp_data_splicer.vhd:8
arp_reply
Definition: arp_reply.vhd:26
DIG_GEC
Definition: DIG_GEC.vhd:25
dataout_mux
Definition: dataout_mux.vhd:8
ip_checksum_calc
Definition: ip_checksum_calc.vhd:26
create_packet
Definition: create_packet.vhd:26
or33
Definition: or33.vhd:8
user_addrs_mux
Definition: user_addrs_mux.vhd:8
filter_data_out
Definition: filter_data_out.vhd:9
dest_info_container
Definition: dest_info_container.vhd:11