otsdaq_prepmodernization  v2_05_02_indev
data_manager.vhd
1 --erased -
2 --erased
3 --erased Comments by rrivera at fnal dot gov : Aug 25, 2015
4 --erased
5 --erased IMPORTANT!! IMPORTANT!!
6 --erased It's very important to note!!!
7 --erased
8 --erased The script that moves these files into a Firmware project will
9 --erased remove all "" comments..
10 --erased The only way (I think) to safely comment is to put "SCRIPT COMMENT OUT" in your comment line with single spacing
11 
12 library ieee;
13 use ieee.std_logic_1164.ALL;
14 use ieee.numeric_std.ALL;
15 
16 entity data_manager is
17  port ( b_data : in std_logic_vector (63 downto 0);
18  b_data_we : in std_logic;
19  b_end_packet : in std_logic;
20  b_mode : in std_logic;
21  four_bit_mode : in std_logic;
22  user_busy : in std_logic;
23  user_crc_err : in std_logic;
24  user_crc_chk : in std_logic;
25 
26  user_rx_data_out : in std_logic_vector (7 downto 0);
27  user_rx_valid_out : in std_logic;
28  user_rx_src_addr : in std_logic_vector (31 downto 0);
29  user_rx_src_mac : in std_logic_vector (47 downto 0);
30  user_rx_src_port : in std_logic_vector (15 downto 0);
31 
32  tx_ctrl_dest_addr : in std_logic_vector (31 downto 0);
33  tx_ctrl_dest_mac : in std_logic_vector (47 downto 0);
34  tx_ctrl_dest_port : in std_logic_vector (15 downto 0);
35  tx_data_dest_addr : in std_logic_vector (31 downto 0);
36  tx_data_dest_mac : in std_logic_vector (47 downto 0);
37  tx_data_dest_port : in std_logic_vector (15 downto 0);
38  user_tx_dest_addr : out std_logic_vector (31 downto 0);
39  user_tx_dest_mac : out std_logic_vector (47 downto 0);
40  user_tx_dest_port : out std_logic_vector (15 downto 0);
41 
42  user_tx_enable_out : in std_logic;
43  user_ready : in std_logic;
44  MASTER_CLK : in std_logic;
45  reset : in std_logic;
46  tx_data : in std_logic_vector (63 downto 0);
47  b_enable : out std_logic;
48  user_tx_trigger : out std_logic;
49  user_tx_data_in : out std_logic_vector (7 downto 0);
50  user_tx_size_in : out std_logic_vector (10 downto 0);
51  ram_addr : out std_logic_vector (63 downto 0);
52  ram_rden : out std_logic;
53  ram_wren : out std_logic;
54  rx_data : out std_logic_vector (63 downto 0));
55 end data_manager;
56 
57 architecture BEHAVIORAL of data_manager is
58 
59  signal clear_delay_count : std_logic;
60  signal crc_err_flag, clear_crc_err_flag : std_logic;
61  signal data_fifo_full : std_logic;
62  signal rx_data_fifo_wren : std_logic;
63  signal rx_data_fifo_wr_data : std_logic_vector (63 downto 0);
64  signal delay_count : std_logic;
65  signal rx_info_fifo_wren : std_logic;
66  signal rx_info_fifo_wr_data : std_logic_vector (15 downto 0);
67  signal rx_data_fifo_empty : std_logic;
68  signal rx_data_fifo_read_enable : std_logic;
69  signal rx_fifo_reset : std_logic;
70  signal rx_fifo_reset_sig : std_logic;
71  signal rx_info_fifo_empty : std_logic;
72  signal rx_info_fifo_full : std_logic;
73  signal rx_data_fifo_full : std_logic;
74  signal rx_info_fifo_rden : std_logic;
75  signal start_delay_count : std_logic;
76  signal tx_data_fifo_din : std_logic_vector (63 downto 0);
77  signal tx_data_fifo_empty : std_logic;
78  signal tx_data_fifo_full : std_logic;
79  signal tx_data_fifo_rden : std_logic;
80  signal tx_data_fifo_read_enable : std_logic;
81  signal tx_data_fifo_wr_en : std_logic;
82  signal tx_info_fifo_rden : std_logic;
83  signal rx_data_sig : std_logic_vector (63 downto 0);
84 
85  signal tx_data_reg : std_logic_vector (63 downto 0);
86  signal rx_data_fifo_rd_data : std_logic_vector (63 downto 0);
87 
88 
89  signal rx_src_addr_fifo_dout : std_logic_vector (47 downto 0);
90  signal rx_src_mac_fifo_dout : std_logic_vector (47 downto 0);
91  signal tx_ctrl_addr_fifo_dout : std_logic_vector (31 downto 0);
92  signal tx_ctrl_port_fifo_dout : std_logic_vector (15 downto 0);
93  signal tx_ctrl_mac_fifo_dout : std_logic_vector (47 downto 0);
94 
95 
96  signal tx_ctrl_fifo_empty : std_logic;
97  signal tx_ctrl_fifo_full : std_logic;
98  signal tx_ctrl_fifo_rden : std_logic;
99  signal tx_ctrl_fifo_read_enable : std_logic;
100 
101  signal tx_ctrl_fifo_wr_en : std_logic;
102  signal tx_ctrl_fifo_reset_sig : std_logic;
103  signal comm_dec_tx_fifo_reset : std_logic;
104  signal tx_seq_ctl_sel : std_logic;
105  signal tx_seq_ret_to_sender : std_logic;
106  signal tx_data_info_fifo_empty : std_logic;
107  signal tx_ctrl_info_fifo_empty : std_logic;
108  signal tx_data_info_fifo_wr_en : std_logic;
109  signal tx_ctrl_info_fifo_wr_en : std_logic;
110 
111  signal tx_data_info_fifo_din : std_logic_vector (15 downto 0);
112  signal tx_data_info_fifo_dout : std_logic_vector (15 downto 0);
113  signal tx_ctrl_info_fifo_din : std_logic_vector (15 downto 0);
114  signal tx_ctrl_info_fifo_dout : std_logic_vector (15 downto 0);
115  signal tx_ctrl_fifo_dout : std_logic_vector (63 downto 0);
116  signal tx_data_fifo_dout : std_logic_vector (63 downto 0);
117  signal rx_info_fifo_rd_data : std_logic_vector (15 downto 0);
118  signal tx_info_fifo_dout : std_logic_vector (15 downto 0);
119  signal tx_seq_data_fifo_dout : std_logic_vector (63 downto 0);
120  signal tx_ctrl_info_fifo_read_enable : std_logic;
121  signal tx_data_info_fifo_read_enable : std_logic;
122  signal tx_data_info_fifo_full : std_logic;
123  signal tx_ctrl_info_fifo_full : std_logic;
124 
125 
126  component DATA_FIFO_0
127  port ( clk : in std_logic;
128  rd_en : in std_logic;
129  srst : in std_logic;
130  wr_en : in std_logic;
131  din : in std_logic_vector (63 downto 0);
132  empty : out std_logic;
133  full : out std_logic;
134  dout : out std_logic_vector (63 downto 0));
135  end component;
136 
137  component INFO_FIFO_0
138  port ( wr_en : in std_logic;
139  clk : in std_logic;
140  srst : in std_logic;
141  din : in std_logic_vector (15 downto 0);
142  rd_en : in std_logic;
143  dout : out std_logic_vector (15 downto 0);
144  empty : out std_logic;
145  full : out std_logic);
146  end component;
147 
148 
149  component ADDR_FIFO
150  port ( wr_en : in std_logic;
151  clk : in std_logic;
152  srst : in std_logic;
153  din : in std_logic_vector (47 downto 0);
154  rd_en : in std_logic;
155  dout : out std_logic_vector (47 downto 0);
156  empty : out std_logic;
157  full : out std_logic);
158  end component;
159 
160 
161 begin
162 
163  rx_data(63 downto 0) <= rx_data_sig(63 downto 0);
164 
165  user_tx_dest_addr <= tx_data_dest_addr when tx_seq_ctl_sel = '1' else
166  tx_ctrl_addr_fifo_dout when tx_seq_ret_to_sender = '1' else
167  tx_ctrl_dest_addr;
168  user_tx_dest_port <= tx_data_dest_port when tx_seq_ctl_sel = '1' else
169  tx_ctrl_port_fifo_dout when tx_seq_ret_to_sender = '1' else
170  tx_ctrl_dest_port;
171  user_tx_dest_mac <= tx_data_dest_mac when tx_seq_ctl_sel = '1' else
172  tx_ctrl_mac_fifo_dout when tx_seq_ret_to_sender = '1' else
173  tx_ctrl_dest_mac;
174 
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310 
311  tx_ctrl_fifo_reset_sig <= comm_dec_tx_fifo_reset or reset;
312 
313 --erased assume there is a select signal from TX_CTRL
314 --erased tx_seq_ctl_sel = 0 for ctrl fifo and 1 for burst data fifo
315  tx_ctrl_fifo_read_enable <= tx_data_fifo_rden when tx_seq_ctl_sel = '0' else '0';
316  tx_data_fifo_read_enable <= tx_data_fifo_rden when tx_seq_ctl_sel = '1' else '0';
317  tx_ctrl_info_fifo_read_enable <= tx_info_fifo_rden when tx_seq_ctl_sel = '0' else '0';
318  tx_data_info_fifo_read_enable <= tx_info_fifo_rden when tx_seq_ctl_sel = '1' else '0';
319  tx_info_fifo_dout <= tx_data_info_fifo_dout when tx_seq_ctl_sel = '1' else tx_ctrl_info_fifo_dout;
320  tx_seq_data_fifo_dout <= tx_data_fifo_dout when tx_seq_ctl_sel = '1' else tx_ctrl_fifo_dout;
321 
322 
323 
324 
325 
326  tx_data_fifo_din <= b_data;
327  rx_fifo_reset_sig <= rx_fifo_reset or reset;
328 
329 
330 
331  RX_DATA_FIFO : DATA_FIFO_0
332  port map (clk =>MASTER_CLK,
333  din(63 downto 0)=>rx_data_fifo_wr_data(63 downto 0),
334  rd_en =>rx_data_fifo_read_enable ,
335  srst =>rx_fifo_reset_sig,
336  wr_en =>rx_data_fifo_wren,
337  dout(63 downto 0)=>rx_data_fifo_rd_data(63 downto 0),
338  empty =>rx_data_fifo_empty,
339  full =>rx_data_fifo_full);
340 
341  RX_DATA_INFO_FIFO : INFO_FIFO_0
342  port map (clk =>MASTER_CLK,
343  din(15 downto 0)=>rx_info_fifo_wr_data(15 downto 0),
344  rd_en =>rx_info_fifo_rden,
345  srst =>rx_fifo_reset_sig,
346  wr_en =>rx_info_fifo_wren,
347  dout(15 downto 0)=>rx_info_fifo_rd_data(15 downto 0),
348  empty =>rx_info_fifo_empty,
349  full =>rx_info_fifo_full);
350 
351  RX_SRC_ADDR_FIFO : ADDR_FIFO
352  port map (clk =>MASTER_CLK,
353  din(31 downto 0)=>user_rx_src_addr(31 downto 0),
354  din(47 downto 32)=>user_rx_src_port(15 downto 0),
355  rd_en =>rx_info_fifo_rden,
356  srst =>rx_fifo_reset_sig,
357  wr_en =>rx_info_fifo_wren,
358  dout(47 downto 0)=>rx_src_addr_fifo_dout(47 downto 0),
359  empty =>open,
360  full =>open);
361 
362  RX_SRC_MAC_FIFO : ADDR_FIFO
363  port map (clk =>MASTER_CLK,
364  din(47 downto 0)=>user_rx_src_mac(47 downto 0),
365  rd_en =>rx_info_fifo_rden,
366  srst =>rx_fifo_reset_sig,
367  wr_en =>rx_info_fifo_wren,
368  dout(47 downto 0)=>rx_src_mac_fifo_dout(47 downto 0),
369  empty =>open,
370  full =>open);
371 
372 
373  TX_DATA_FIFO : DATA_FIFO_0
374  port map (clk =>MASTER_CLK,
375  din(63 downto 0)=>tx_data_fifo_din(63 downto 0),
376  rd_en =>tx_data_fifo_read_enable,
377  srst =>reset,
378  wr_en =>tx_data_fifo_wr_en ,
379  dout(63 downto 0)=>tx_data_fifo_dout(63 downto 0),
380  empty =>tx_data_fifo_empty ,
381  full =>tx_data_fifo_full );
382 
383  TX_DATA_INFO_FIFO : INFO_FIFO_0
384  port map (clk =>MASTER_CLK,
385  din(15 downto 0)=>tx_data_info_fifo_din(15 downto 0),
386  rd_en=>tx_data_info_fifo_read_enable ,
387  srst =>reset,
388  wr_en=>tx_data_info_fifo_wr_en,
389  dout(15 downto 0)=>tx_data_info_fifo_dout(15 downto 0),
390  empty=>tx_data_info_fifo_empty,
391  full =>tx_data_info_fifo_full );
392 
393  TX_CTRL_FIFO : DATA_FIFO_0
394  port map (clk =>MASTER_CLK,
395  din(63 downto 0)=>tx_data(63 downto 0),
396  rd_en =>tx_ctrl_fifo_read_enable,
397  srst =>tx_ctrl_fifo_reset_sig,
398  wr_en =>tx_ctrl_fifo_wr_en ,
399  dout(63 downto 0)=>tx_ctrl_fifo_dout(63 downto 0),
400  empty =>tx_ctrl_fifo_empty ,
401  full =>tx_ctrl_fifo_full );
402 
403  TX_CTRL_INFO_FIFO : INFO_FIFO_0
404  port map (clk =>MASTER_CLK,
405  din(15 downto 0)=>tx_ctrl_info_fifo_din(15 downto 0),
406  rd_en=>tx_ctrl_info_fifo_read_enable ,
407  srst =>tx_ctrl_fifo_reset_sig ,
408  wr_en=>tx_ctrl_info_fifo_wr_en,
409  dout(15 downto 0)=>tx_ctrl_info_fifo_dout(15 downto 0),
410  empty=>tx_ctrl_info_fifo_empty,
411  full =>tx_ctrl_info_fifo_full );
412 
413  TX_CTRL_ADDR_FIFO : ADDR_FIFO
414  port map (clk =>MASTER_CLK,
415  din(47 downto 0)=>rx_src_addr_fifo_dout(47 downto 0),
416  rd_en=>tx_ctrl_info_fifo_read_enable ,
417  srst =>tx_ctrl_fifo_reset_sig ,
418  wr_en=>tx_ctrl_info_fifo_wr_en,
419  dout(31 downto 0)=>tx_ctrl_addr_fifo_dout(31 downto 0),
420  dout(47 downto 32)=>tx_ctrl_port_fifo_dout(15 downto 0),
421  empty=>open,
422  full =>open);
423 
424  TX_CTRL_MAC_FIFO : ADDR_FIFO
425  port map (clk =>MASTER_CLK,
426  din(47 downto 0)=>rx_src_mac_fifo_dout(47 downto 0),
427  rd_en=>tx_ctrl_info_fifo_read_enable ,
428  srst =>tx_ctrl_fifo_reset_sig ,
429  wr_en=>tx_ctrl_info_fifo_wr_en,
430  dout(47 downto 0)=>tx_ctrl_mac_fifo_dout(47 downto 0),
431  empty=>open,
432  full =>open);
433 
434  burst_controller_sm : entity work.burst_controller_sm
435  port map (
436  b_data_we =>b_data_we,
437  b_end_packet =>b_end_packet,
438  b_mode =>b_mode,
439  clk =>MASTER_CLK ,
440  reset =>reset,
441  tx_data_full =>tx_data_fifo_full ,
442  tx_info_full =>tx_data_info_fifo_full,
443  b_enable =>b_enable,
444  tx_data_we =>tx_data_fifo_wr_en ,
445  tx_info(15 downto 0)=>tx_data_info_fifo_din(15 downto 0),
446  tx_info_we =>tx_data_info_fifo_wr_en);
447 
448 
449  GEC_RX_CTRL : entity work.rx_ctl
450  port map (
451  clock =>MASTER_CLK ,
452  four_bit_mode =>four_bit_mode,
453  user_crc_err =>user_crc_err,
454  user_crc_chk =>user_crc_chk,
455  user_rx_data_out(7 downto 0)=>user_rx_data_out(7 downto 0),
456  user_rx_valid_out =>user_rx_valid_out ,
457  reset =>reset,
458  crc_err_flag =>crc_err_flag,
459  clear_crc_err_flag =>clear_crc_err_flag ,
460  data_fifo_wdata(63 downto 0)=>rx_data_fifo_wr_data(63 downto 0),
461  data_fifo_wren =>rx_data_fifo_wren ,
462  info_fifo_wren =>rx_info_fifo_wren ,
463  info_fifo_wr_data(15 downto 0)=>rx_info_fifo_wr_data(15 downto 0));
464 
465 
466  RAM_COMM_DEC : entity work.ram_comm_dec
467  port map (
468  clock =>MASTER_CLK ,
469  reset =>reset,
470  rx_data_fifo_rd_data(63 downto 0)=>rx_data_fifo_rd_data(63 downto 0),
471  ram_wdata(63 downto 0)=>rx_data_sig(63 downto 0),
472  rx_info_fifo_empty =>rx_info_fifo_empty ,
473  rx_info_fifo_full =>rx_info_fifo_full,
474  rx_data_fifo_full =>rx_data_fifo_full,
475  rx_info_fifo_rd_data(15 downto 0)=>rx_info_fifo_rd_data(15 downto 0),
476  tx_info_fifo_full =>tx_ctrl_info_fifo_full,
477  ram_addr(63 downto 0)=>ram_addr(63 downto 0),
478  ram_rden =>ram_rden,
479  ram_wren =>ram_wren,
480  user_ready =>user_ready,
481  user_rx_valid_out =>user_rx_valid_out,
482  crc_err_flag =>crc_err_flag,
483  clear_crc_err_flag =>clear_crc_err_flag ,
484  rx_data_fifo_rden =>rx_data_fifo_read_enable,
485  Rx_FIFO_Reset =>rx_fifo_reset,
486  rx_info_fifo_rden =>rx_info_fifo_rden ,
487  tx_data_fifo_wren =>tx_ctrl_fifo_wr_en ,
488  Tx_FIFO_Reset =>comm_dec_tx_fifo_reset,
489 
490  tx_info_fifo_wren =>tx_ctrl_info_fifo_wr_en,
491  tx_info_fifo_wr_data(15 downto 0)=>tx_ctrl_info_fifo_din(15 downto 0));
492 
493  GEC_TX_SEQ_CTL : entity work.tx_seq_ctl
494  port map (
495  reset =>reset,
496  clk =>MASTER_CLK ,
497  four_bit_mode =>four_bit_mode,
498 
499  dest_busy =>user_busy,
500  user_trigger =>user_tx_trigger,
501  user_tx_enable_out =>user_tx_enable_out ,
502  tx_data(7 downto 0)=>user_tx_data_in(7 downto 0),
503  user_tx_size_in(10 downto 0)=>user_tx_size_in(10 downto 0),
504 
505  fifo_sel =>tx_seq_ctl_sel,
506  ret_to_sender =>tx_seq_ret_to_sender ,
507 
508  data_fifo_empty =>tx_data_fifo_empty ,
509  data_fifo_rd_data(63 downto 0)=>tx_seq_data_fifo_dout(63 downto 0),
510  data_fifo_rden =>tx_data_fifo_rden ,
511 
512  data_info_fifo_empty =>tx_data_info_fifo_empty,
513  ctrl_info_fifo_empty =>tx_ctrl_info_fifo_empty,
514 
515  info_fifo_rd_data(15 downto 0)=>tx_info_fifo_dout(15 downto 0),
516  info_fifo_rden =>tx_info_fifo_rden );
517 
518 
519 
520 end BEHAVIORAL;
521 
522 
523 
524 
INFO_FIFO_0
Definition: INFO_FIFO_0.vhd:43
burst_controller_sm
Definition: burst_controller_sm.vhd:26
ADDR_FIFO
Definition: ADDR_FIFO.vhd:43
DATA_FIFO_0
Definition: DATA_FIFO_0.vhd:43
data_manager
Definition: data_manager.vhd:16
tx_seq_ctl
Definition: tx_seq_ctl.vhd:26
rx_ctl
Definition: rx_ctl.vhd:26
ram_comm_dec
Definition: ram_comm_dec.vhd:26