DATA_FIFO_0.vhd

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-- You must compile the wrapper file DATA_FIFO_0.vhd when simulating
-- the core, DATA_FIFO_0. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".

-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
Library XilinxCoreLib;
-- synthesis translate_on
ENTITY DATA_FIFO_0 IS
    port (
    clk: IN std_logic;
    din: IN std_logic_VECTOR(63 downto 0);
    rd_en: IN std_logic;
    srst: IN std_logic;
    wr_en: IN std_logic;
    dout: OUT std_logic_VECTOR(63 downto 0);
    empty: OUT std_logic;
    full: OUT std_logic);
END DATA_FIFO_0;

ARCHITECTURE DATA_FIFO_0_a OF DATA_FIFO_0 IS
-- synthesis translate_off
component wrapped_DATA_FIFO_0
    port (
    clk: IN std_logic;
    din: IN std_logic_VECTOR(63 downto 0);
    rd_en: IN std_logic;
    srst: IN std_logic;
    wr_en: IN std_logic;
    dout: OUT std_logic_VECTOR(63 downto 0);
    empty: OUT std_logic;
    full: OUT std_logic);
end component;

-- Configuration specification 
    for all : wrapped_DATA_FIFO_0 use entity XilinxCoreLib.fifo_generator_v4_3(behavioral)
        generic map(
            c_has_int_clk  => 0,
            c_rd_freq  => 1,
            c_wr_response_latency  => 1,
            c_has_srst  => 1,
            c_has_rd_data_count => 0,
            c_din_width  => 64,
            c_has_wr_data_count => 0,
            c_full_flags_rst_val  => 0,
            c_implementation_type  => 0,
            c_family  => "virtex4",
            c_use_embedded_reg  => 0,
            c_has_wr_rst  => 0,
            c_wr_freq  => 1,
            c_use_dout_rst  => 0,
            c_underflow_low  => 0,
            c_has_meminit_file  => 0,
            c_has_overflow  => 0,
            c_preload_latency  => 1,
            c_dout_width  => 64,
            c_msgon_val  => 1,
            c_rd_depth  => 256,
            c_default_value  => "BlankString",
            c_mif_file_name  => "BlankString",
            c_has_underflow  => 0,
            c_has_rd_rst  => 0,
            c_has_almost_full  => 0,
            c_has_rst  => 0,
            c_data_count_width  => 8,
            c_has_wr_ack  => 0,
            c_use_ecc  => 0,
            c_wr_ack_low  => 0,
            c_common_clock  => 1,
            c_rd_pntr_width  => 8,
            c_use_fwft_data_count  => 0,
            c_has_almost_empty  => 0,
            c_rd_data_count_width  => 8,
            c_enable_rlocs  => 0,
            c_wr_pntr_width  => 8,
            c_overflow_low  => 0,
            c_prog_empty_type  => 0,
            c_optimization_mode => 0,
            c_wr_data_count_width  => 8,
            c_preload_regs  => 0,
            c_dout_rst_val  => "0",
            c_has_data_count  => 0,
            c_prog_full_thresh_negate_val  => 253,
            c_wr_depth  => 256,
            c_prog_empty_thresh_negate_val  => 3,
            c_prog_empty_thresh_assert_val  => 2,
            c_has_valid  => 0,
            c_init_wr_pntr_val  => 0,
            c_prog_full_thresh_assert_val  => 254,
            c_use_fifo16_flags  => 0,
            c_has_backup  => 0,
            c_valid_low  => 0,
            c_prim_fifo_type  => "512x72",
            c_count_type  => 0,
            c_prog_full_type  => 0,
            c_memory_type  => 1);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_DATA_FIFO_0
        port map (
            clk  => clk,
            din  => din,
            rd_en  => rd_en,
            srst  => srst,
            wr_en  => wr_en,
            dout  => dout,
            empty  => empty,
            full  => full);
-- synthesis translate_on

END DATA_FIFO_0_a;