otsdaq_prepmodernization  v2_05_02_indev
rx_ctl.vhd
1 -------------------------------------------------------------------------------
2 --
3 -- Title : GEC_RX_CTL
4 -- Design : ethernet_controller
5 -- Author : aprosser
6 -- Company : CD_CEPA_ESE
7 --
8 -------------------------------------------------------------------------------
9 --
10 -- File : d:\Projects\otsdaq\OtS Ethernet MAC firmware\ActiveHDL_proj\ethernet_controller\compile\rx_ctl.vhd
11 -- Generated : 02/29/16 11:09:25
12 -- From : d:/Projects/otsdaq/OtS Ethernet MAC firmware/ActiveHDL_proj/ethernet_controller/src/rx_ctl.asf
13 -- By : FSM2VHDL ver. 5.0.7.2
14 --
15 -------------------------------------------------------------------------------
16 --
17 -- Description :
18 --
19 -------------------------------------------------------------------------------
20 
21 library IEEE;
22 use IEEE.std_logic_1164.all;
23 use ieee.numeric_std.all;
24 use work.params_package.all;
25 
26 entity rx_ctl is
27  port (
28  clear_crc_err_flag: in STD_LOGIC;
29  clock: in STD_LOGIC;
30  four_bit_mode: in STD_LOGIC;
31  reset: in STD_LOGIC;
32  user_crc_chk: in STD_LOGIC;
33  user_crc_err: in STD_LOGIC;
34  user_rx_data_out: in STD_LOGIC_VECTOR (7 downto 0);
35  user_rx_valid_out: in STD_LOGIC;
36  crc_err_flag: out STD_LOGIC;
37  data_fifo_wdata: out STD_LOGIC_VECTOR (63 downto 0);
38  data_fifo_wren: out STD_LOGIC;
39  info_fifo_wr_data: out STD_LOGIC_VECTOR (15 downto 0);
40  info_fifo_wren: out STD_LOGIC);
41 end rx_ctl;
42 
43 architecture arch of rx_ctl is
44 
45 -- diagram signals declarations
46 signal clken: STD_LOGIC;
47 signal com_code: STD_LOGIC;
48 signal crc_err_reg: STD_LOGIC;
49 signal data_fifo_wdata_sig: STD_LOGIC_VECTOR (63 downto 0);
50 signal data_fifo_wren_sig: STD_LOGIC;
51 signal info_fifo_wren_sig: STD_LOGIC;
52 signal q_w_count: UNSIGNED (7 downto 0);
53 signal q_w_counter: UNSIGNED (7 downto 0);
54 
55 -- BINARY ENCODED state machine: Sreg0
56 attribute ENUM_ENCODING: string;
57 type Sreg0_type is (
58  idle, insert_crc, rcvdone, S13, S3_S4, S3_S9, S3_S8, S3_S7, S3_S6, S3_S5, S3_S11, S3_S10
59 );
60 attribute ENUM_ENCODING of Sreg0_type: type is
61  "0000 " & -- idle
62  "0001 " & -- insert_crc
63  "0010 " & -- rcvdone
64  "0011 " & -- S13
65  "0100 " & -- S3_S4
66  "0101 " & -- S3_S9
67  "0110 " & -- S3_S8
68  "0111 " & -- S3_S7
69  "1000 " & -- S3_S6
70  "1001 " & -- S3_S5
71  "1010 " & -- S3_S11
72  "1011" ; -- S3_S10
73 
74 signal Sreg0: Sreg0_type;
75 
76 attribute STATE_VECTOR: string;
77 attribute STATE_VECTOR of arch: architecture is "Sreg0";
78 
79 begin
80 
81 -- concurrent signals assignments
82 
83 -- Diagram ACTION
84 info_fifo_wren <= info_fifo_wren_sig and clken;
85 data_fifo_wren <= data_fifo_wren_sig and clken;
86 data_fifo_wdata <= data_fifo_wdata_sig;
87 four_bit_proc : process (clock) -- make trigger sig a single clock width pulse
88 begin
89  if rising_edge(clock) then
90  if (four_bit_mode = '1') then
91  clken <= not clken;
92  else
93  clken <= '1';
94  end if;
95  end if;
96 end process;
97 crc_err_proc : process (clock) -- register crc err after reset
98 begin
99  if rising_edge(clock) then
100  if (reset = '1') then
101  crc_err_reg <= '0';
102  crc_err_flag <= '0';
103  elsif (user_crc_err = '1') then
104  crc_err_reg <= '1';
105  --stay high until reset to indicate there was an error ever
106  crc_err_flag <= '1';
107  elsif (clear_crc_err_flag = '1') then -- command handler clears err flag after reseting fifos
108  crc_err_flag <= '0';
109  end if;
110  end if;
111 end process;
112 
113 ----------------------------------------------------------------------
114 -- Machine: Sreg0
115 ----------------------------------------------------------------------
116 Sreg0_machine: process (clock)
117 begin
118  if clock'event and clock = '1' then
119  if reset = '1' then
120  Sreg0 <= idle;
121  -- Set default values for outputs, signals and variables
122  data_fifo_wren_sig <= '0';
123  info_fifo_wren_sig <= '0';
124  info_fifo_wr_data(7 downto 0) <= (others=>'0');
125  com_code <= '0';
126  q_w_count <= (others=>'0');
127  q_w_counter <= (others=>'0');
128  data_fifo_wdata_sig <= (others=>'0');
129  else
130  if clken = '1' then
131  -- Set default values for outputs, signals and variables
132  data_fifo_wren_sig <= '0';
133  info_fifo_wren_sig <= '0';
134  case Sreg0 is
135  when idle =>
136  if user_rx_valid_out = '1' then
137  Sreg0 <= S13;
138  -- Put the entire command/size word in the info FIFO.
139  -- This is not written until all info for the fifo is accumulated.
140  info_fifo_wr_data(7 downto 0) <= user_rx_data_out;
141  com_code <= user_rx_data_out(0);
142  -- save command code
143  end if;
144  when insert_crc =>
145  if user_crc_chk = '1' then -- it's possible that there was an error in the protocol that was sent.. -- and so must wait for transimission to complete
146  Sreg0 <= rcvdone;
147  end if;
148  when rcvdone =>
149  Sreg0 <= idle;
150  info_fifo_wr_data(7) <= crc_err_reg;
151  -- return the crc error status in info, info complete
152  info_fifo_wren_sig <= '1';
153  -- we actually write the info fifo here.
154  when S13 =>
155  if (unsigned(user_rx_data_out) = 0) -- size is 0
156  and (user_rx_valid_out = '1') then -- multi-operation packet
157  Sreg0 <= idle;
158  info_fifo_wr_data(15 downto 8) <= user_rx_data_out;
159  info_fifo_wr_data(7) <= crc_err_reg;
160  -- return the crc error status in info, info complete
161  info_fifo_wren_sig <= '1';
162  -- we actually write the info fifo here.
163  elsif unsigned(user_rx_data_out) = 0 then -- size is 0
164  Sreg0 <= insert_crc;
165  info_fifo_wr_data(15 downto 8) <= user_rx_data_out;
166  else
167  Sreg0 <= S3_S4;
168  info_fifo_wr_data(15 downto 8) <= user_rx_data_out;
169  q_w_counter <= (others => '0');
170  -- initialize the counter
171  -- Increment the quad word count for writes
172  -- First word is the starting address
173  -- next n words (I received a count of n)
174  -- is the actual quad word data for writing.
175  if (com_code = '1') then --write data coming
176  q_w_count <= unsigned(user_rx_data_out) + 1;
177  -- watch out for overflow
178  -- writes the starting address first plus the
179  -- data
180  else -- all other commands only have 1
181  q_w_count <= (0=>'1',others => '0');
182  -- This will cause only the address word
183  -- to be written to the data fifo.
184  end if;
185  end if;
186  when S3_S4 =>
187  Sreg0 <= S3_S5;
188  -- Finish the write to the data fifo
189  data_fifo_wdata_sig <= user_rx_data_out & data_fifo_wdata_sig(63 downto 8);
190  q_w_counter <= q_w_counter + 1;
191  -- increment the counter
192  when S3_S9 =>
193  Sreg0 <= S3_S10;
194  data_fifo_wdata_sig <= user_rx_data_out & data_fifo_wdata_sig(63 downto 8);
195  when S3_S8 =>
196  Sreg0 <= S3_S9;
197  data_fifo_wdata_sig <= user_rx_data_out & data_fifo_wdata_sig(63 downto 8);
198  when S3_S7 =>
199  Sreg0 <= S3_S8;
200  data_fifo_wdata_sig <= user_rx_data_out & data_fifo_wdata_sig(63 downto 8);
201  when S3_S6 =>
202  Sreg0 <= S3_S7;
203  data_fifo_wdata_sig <= user_rx_data_out & data_fifo_wdata_sig(63 downto 8);
204  when S3_S5 =>
205  Sreg0 <= S3_S6;
206  data_fifo_wdata_sig <= user_rx_data_out & data_fifo_wdata_sig(63 downto 8);
207  when S3_S11 =>
208  if (q_w_counter = q_w_count) and (user_rx_valid_out = '1') then -- multi-operation packet
209  Sreg0 <= idle;
210  data_fifo_wren_sig <= '1';
211  -- write the assembled data to the FIFO
212  data_fifo_wdata_sig <= user_rx_data_out & data_fifo_wdata_sig(63 downto 8);
213  info_fifo_wr_data(7) <= crc_err_reg;
214  -- return the crc error status in info, info complete
215  info_fifo_wren_sig <= '1';
216  -- we actually write the info fifo here.
217  elsif q_w_counter = q_w_count then
218  Sreg0 <= insert_crc;
219  data_fifo_wren_sig <= '1';
220  -- write the assembled data to the FIFO
221  data_fifo_wdata_sig <= user_rx_data_out & data_fifo_wdata_sig(63 downto 8);
222  else
223  Sreg0 <= S3_S4;
224  data_fifo_wren_sig <= '1';
225  -- write the assembled data to the FIFO
226  data_fifo_wdata_sig <= user_rx_data_out & data_fifo_wdata_sig(63 downto 8);
227  end if;
228  when S3_S10 =>
229  Sreg0 <= S3_S11;
230  data_fifo_wdata_sig <= user_rx_data_out & data_fifo_wdata_sig(63 downto 8);
231 --vhdl_cover_off
232  when others =>
233  null;
234 --vhdl_cover_on
235  end case;
236  end if;
237  end if;
238  end if;
239 end process;
240 
241 end arch;
rx_ctl
Definition: rx_ctl.vhd:26