otsdaq_prepmodernization  v2_05_02_indev
ethernet_controller_wrapper.vhd
1 -------------------------------------------------------------------------------
2 --
3 -- Title : ethernet_controller_wrapper
4 -- Design : ethernet_controller
5 -- Author : rrivera at fnal dot gov
6 -- Company : Fermi National Accelerator Laboratory
7 --
8 -------------------------------------------------------------------------------
9 --
10 -- Modified : Thu Nov 12 10:33:07 2015
11 --
12 -------------------------------------------------------------------------------
13 --
14 -- Description :
15 --
16 -------------------------------------------------------------------------------
17 -- Design unit header --
18 library IEEE;
19 use ieee.std_logic_1164.ALL;
20 use ieee.numeric_std.ALL;
21 
22 
23 
24 entity ethernet_controller_wrapper is
25  port(
26  reset : in STD_LOGIC;
27  user_busy : out STD_LOGIC;
28 
29  GMII_RX_CLK : in STD_LOGIC;
30 
31  GMII_RX_DV : in STD_LOGIC;
32  GMII_RXD : in STD_LOGIC_VECTOR(7 downto 0);
33  GMII_RX_ER : in STD_LOGIC;
34  GMII_TX_EN : out STD_LOGIC;
35  GMII_TXD : out STD_LOGIC_VECTOR(7 downto 0);
36  GMII_TX_ER : out STD_LOGIC;
37  GTX_CLK : out STD_LOGIC;
38 
39  self_addr : in STD_LOGIC_VECTOR(31 downto 0);
40  self_mac : in STD_LOGIC_VECTOR(47 downto 0);
41  self_port : in STD_LOGIC_VECTOR(15 downto 0);
42  arp_announce : in STD_LOGIC;
43 
44  user_tx_dest_addr : in STD_LOGIC_VECTOR(31 downto 0);
45  user_tx_dest_mac : in STD_LOGIC_VECTOR(47 downto 0);
46  user_tx_dest_port : in STD_LOGIC_VECTOR(15 downto 0);
47 
48 
49  user_rx_valid_out : out STD_LOGIC;
50  user_rx_data_out : out STD_LOGIC_VECTOR(7 downto 0);
51  user_rx_size_out : out STD_LOGIC_VECTOR(10 downto 0);
52  user_tx_enable_out : out STD_LOGIC;
53  user_tx_data_in : in STD_LOGIC_VECTOR(7 downto 0);
54  user_tx_size_in : in STD_LOGIC_VECTOR(10 downto 0);
55  user_tx_trigger : in STD_LOGIC;
56 
57  crc_err : out STD_LOGIC;
58  crc_chk_out : out STD_LOGIC;
59  four_bit_mode_out : out STD_LOGIC;
60 
61  udp_fwd_port : out STD_LOGIC_VECTOR(15 downto 0);
62 
63  user_rx_src_capture_for_ctrl : out STD_LOGIC;
64  user_rx_src_capture_for_data : out STD_LOGIC;
65  user_rx_src_addr : out STD_LOGIC_VECTOR(31 downto 0);
66  user_rx_src_mac : out STD_LOGIC_VECTOR(47 downto 0);
67  user_rx_src_port : out STD_LOGIC_VECTOR(15 downto 0)
68  );
69 end entity ;
70 
71 architecture arch of ethernet_controller_wrapper is
72 
73  ---- Verilog Component declarations ----
74  component crc_chk
75  port (
76  CRC_chk_en : in STD_LOGIC;
77  CRC_data : in STD_LOGIC_VECTOR(7 downto 0);
78  CRC_en : in STD_LOGIC;
79  CRC_init : in STD_LOGIC;
80  Clk : in STD_LOGIC;
81  Reset : in STD_LOGIC;
82  CRC_err : out STD_LOGIC
83  );
84  end component;
85  component crc_gen
86  port (
87  CRC_rd : in STD_LOGIC;
88  Clk : in STD_LOGIC;
89  Data_en : in STD_LOGIC;
90  Frame_data : in STD_LOGIC_VECTOR(7 downto 0);
91  Init : in STD_LOGIC;
92  Reset : in STD_LOGIC;
93  CRC_end : out STD_LOGIC;
94  CRC_out : out STD_LOGIC_VECTOR(7 downto 0)
95  );
96  end component;
97 
98  ---- Signal declarations ----
99 
100  signal crc_chk_en : STD_LOGIC;
101  signal crc_chk_init : STD_LOGIC;
102  signal crc_chk_rd : STD_LOGIC;
103  signal crc_gen_en : STD_LOGIC;
104  signal crc_gen_en_masked : STD_LOGIC;
105  signal crc_gen_init : STD_LOGIC;
106  signal crc_gen_rd : STD_LOGIC;
107  signal crc_gen_rd_masked : STD_LOGIC;
108  signal crc_mask : STD_LOGIC;
109  signal four_bit_mode : STD_LOGIC;
110  signal rx_dv_handled : STD_LOGIC;
111  signal rx_er_handled : STD_LOGIC;
112  signal tx_dv : STD_LOGIC;
113  signal tx_dv_out : STD_LOGIC;
114  signal tx_er : STD_LOGIC;
115  signal tx_er_out : STD_LOGIC;
116  signal crc_chk_din : STD_LOGIC_VECTOR(7 downto 0);
117  signal crc_gen_out : STD_LOGIC_VECTOR(7 downto 0);
118  signal GMII_RXD_sig : STD_LOGIC_VECTOR(7 downto 0);
119  signal rx_data_handled : STD_LOGIC_VECTOR(7 downto 0);
120  signal txd : STD_LOGIC_VECTOR(7 downto 0);
121  signal txd_out : STD_LOGIC_VECTOR(7 downto 0);
122 
123 
124 
125 begin
126 
127  ---- Component instantiations ----
128 
129  ethernet_controller : entity work.ethernet_controller
130  port map(
131  GMII_GTX_CLK => GTX_CLK,
132  GMII_RXD => rx_data_handled,
133  GMII_RX_CLK => GMII_RX_CLK,
134  GMII_RX_DV => rx_dv_handled,
135  GMII_RX_ER => rx_er_handled,
136  GMII_TXD => txd,
137  GMII_TX_EN => tx_dv,
138  GMII_TX_ER => tx_er,
139 
140  four_bit_mode_out => four_bit_mode,
141  reset => reset,
142 
143  self_addr => self_addr,
144  self_mac => self_mac,
145  self_port => self_port,
146  busy => user_busy,
147  trigger => user_tx_trigger ,
148  dest_addr => user_tx_dest_addr ,
149  dest_mac => user_tx_dest_mac ,
150  dest_port => user_tx_dest_port ,
151  arp_announce => arp_announce,
152 
153  src_addr => user_rx_src_addr ,
154  src_mac => user_rx_src_mac ,
155  src_port => user_rx_src_port ,
156  src_capture_for_ctrl => user_rx_src_capture_for_ctrl ,
157  src_capture_for_data => user_rx_src_capture_for_data ,
158 
159  crc_chk_din => crc_chk_din,
160  crc_chk_en => crc_chk_en,
161  crc_chk_init => crc_chk_init,
162  crc_chk_rd => crc_chk_rd,
163  crc_gen_en => crc_gen_en,
164  crc_gen_init => crc_gen_init,
165  crc_gen_rd => crc_gen_rd,
166 
167  udp_dest_port => udp_fwd_port, --could be used as additional address space for user firmware
168 
169  en_tx_data => user_tx_enable_out ,
170  udp_data_count => user_rx_size_out,
171  user_rx_data_out => user_rx_data_out ,
172  user_rx_valid_out => user_rx_valid_out ,
173  user_tx_data_in => user_tx_data_in,
174  user_tx_size_in => user_tx_size_in
175  );
176 
177  xgmii : entity work.MII_100_1000_handler
178  port map(
179  clk => GMII_RX_CLK,
180  reset => reset,
181  rx_data => GMII_RXD,
182  rx_data_handled => rx_data_handled,
183  rx_dv => GMII_RX_DV,
184  rx_dv_handled => rx_dv_handled,
185  rx_er => GMII_RX_ER,
186  rx_er_handled => rx_er_handled,
187  tx_data => txd_out,
188  tx_data_handled => GMII_TXD,
189  tx_dv => tx_dv_out,
190  tx_dv_handled => GMII_TX_EN,
191  tx_er => tx_er_out,
192  tx_er_handled => GMII_TX_ER
193  );
194 
195  crc_gen_en_masked <= crc_gen_en and crc_mask;
196 
197  crc_gen_rd_masked <= crc_gen_rd and crc_mask;
198 
199  crc_chk_out <= crc_chk_rd; --output moment of checking, so downstream users know when check is complete
200 
201  crcChk : crc_chk --Verilog component
202  port map(
203  CRC_chk_en => crc_chk_rd,
204  CRC_data => crc_chk_din,
205  CRC_en => crc_chk_en,
206  CRC_err => crc_err,
207  CRC_init => crc_chk_init,
208  Clk => GMII_RX_CLK,
209  Reset => reset
210  );
211 
212  crcGen : crc_gen --Verilog component
213  port map(
214  CRC_out => crc_gen_out,
215  CRC_rd => crc_gen_rd_masked ,
216  Clk => GMII_RX_CLK,
217  Data_en => crc_gen_en_masked ,
218  Frame_data => txd,
219  Init => crc_gen_init,
220  Reset => reset
221  );
222 
223  genDbgCRC:for i in 0 to 0 generate
224  signal tmp_rd_sig: std_logic := '0';
225  signal tmp_cnt : unsigned (1 downto 0) := (others => '0');
226  begin
227 
228  process(GMII_RX_CLK)
229  begin
230  if (rising_edge(GMII_RX_CLK)) then
231  tmp_rd_sig <= '0';
232  if crc_chk_rd = '1' then
233  tmp_rd_sig <= '1';
234  tmp_cnt <= "11";
235  elsif tmp_cnt /= 0 then
236  tmp_rd_sig <= '1';
237  tmp_cnt <= tmp_cnt - 1;
238  end if;
239  end if;
240 
241  end process;
242 
243  crcGenDebug : crc_gen --Verilog component for debuggin
244  port map(
245  CRC_out => open,
246  CRC_rd => tmp_rd_sig,
247  Clk => GMII_RX_CLK,
248  Data_en => crc_chk_en,
249  Frame_data => crc_chk_din,
250  Init => crc_chk_init,
251  Reset => reset
252  );
253  end generate;
254 
255  crcSplice : entity work.crc_splice
256  port map(
257  clk => GMII_RX_CLK,
258  crc => crc_gen_out,
259  crc_mask => crc_mask,
260  data => txd,
261  four_bit_mode => four_bit_mode,
262  rd => crc_gen_rd,
263  tx_en => tx_dv_out,
264  tx_en_in => tx_dv,
265  tx_er => tx_er_out,
266  tx_er_in => tx_er,
267  txd => txd_out
268  );
269 
270 
271  ---- Terminal assignment ----
272 
273  -- Output\buffer terminals
274  four_bit_mode_out <= four_bit_mode;
275 
276 
277 end arch;
ethernet_controller_wrapper
Definition: ethernet_controller_wrapper.vhd:24
MII_100_1000_handler
Definition: xmii_handler.vhd:25
ethernet_controller
Definition: ethernet_controller.vhd:25
crc_splice
Definition: crc_splice.vhd:18