fifo_adc_exdes.vhd

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--
-- FIFO Generator Core - core top file for implementation
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
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--
-- Filename: fifo_adc_exdes.vhd
--
-- Description:
--   This is the FIFO core wrapper with BUFG instances for clock connections.
--
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-- Library Declarations
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

library unisim;
use unisim.vcomponents.all;

--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity fifo_adc_exdes is
   PORT (
           WR_CLK                    : IN  std_logic;
           RD_CLK                    : IN  std_logic;
           WR_DATA_COUNT             : OUT std_logic_vector(10-1 DOWNTO 0);
           RD_DATA_COUNT             : OUT std_logic_vector(8-1 DOWNTO 0);
           RST                       : IN  std_logic;
           OVERFLOW                  : OUT std_logic;
           WR_EN             : IN  std_logic;
           RD_EN                     : IN  std_logic;
           DIN                       : IN  std_logic_vector(16-1 DOWNTO 0);
           DOUT                      : OUT std_logic_vector(64-1 DOWNTO 0);
           FULL                      : OUT std_logic;
           EMPTY                     : OUT std_logic);

end fifo_adc_exdes;



architecture xilinx of fifo_adc_exdes is

  signal wr_clk_i : std_logic;
  signal rd_clk_i : std_logic;



  component fifo_adc is
   PORT (
           WR_CLK                    : IN  std_logic;
           RD_CLK                    : IN  std_logic;
           WR_DATA_COUNT             : OUT std_logic_vector(10-1 DOWNTO 0);
           RD_DATA_COUNT             : OUT std_logic_vector(8-1 DOWNTO 0);
           RST                       : IN  std_logic;
           OVERFLOW                  : OUT std_logic;
           WR_EN             : IN  std_logic;
           RD_EN                     : IN  std_logic;
           DIN                       : IN  std_logic_vector(16-1 DOWNTO 0);
           DOUT                      : OUT std_logic_vector(64-1 DOWNTO 0);
           FULL                      : OUT std_logic;
           EMPTY                     : OUT std_logic);

  end component;


begin

  wr_clk_buf: bufg
    PORT map(
      i  => WR_CLK,
      o  => wr_clk_i
      );

  rd_clk_buf: bufg
    PORT map(
      i  => RD_CLK,
      o  => rd_clk_i
      );


  exdes_inst : fifo_adc 
    PORT MAP (
           WR_CLK                     => wr_clk_i,
           RD_CLK                     => rd_clk_i,
           WR_DATA_COUNT              => wr_data_count,
           RD_DATA_COUNT              => rd_data_count,
           RST                        => rst,
           OVERFLOW                   => overflow,
           WR_EN              => wr_en,
           RD_EN                      => rd_en,
           DIN                        => din,
           DOUT                       => dout,
           FULL                       => full,
           EMPTY                      => empty);

end xilinx;