otsdaq_prepmodernization  v2_05_02_indev
fifo_adc.vhd
1 --------------------------------------------------------------------------------
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27 --------------------------------------------------------------------------------
28 --------------------------------------------------------------------------------
29 -- You must compile the wrapper file fifo_adc.vhd when simulating
30 -- the core, fifo_adc. When compiling the wrapper file, be sure to
31 -- reference the XilinxCoreLib VHDL simulation library. For detailed
32 -- instructions, please refer to the "CORE Generator Help".
33 
34 -- The synthesis directives "translate_off/translate_on" specified
35 -- below are supported by Xilinx, Mentor Graphics and Synplicity
36 -- synthesis tools. Ensure they are correct for your synthesis tool(s).
37 
38 LIBRARY ieee;
39 USE ieee.std_logic_1164.ALL;
40 -- synthesis translate_off
41 LIBRARY XilinxCoreLib;
42 -- synthesis translate_on
43 ENTITY fifo_adc IS
44  PORT (
45  rst : IN STD_LOGIC;
46  wr_clk : IN STD_LOGIC;
47  rd_clk : IN STD_LOGIC;
48  din : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
49  wr_en : IN STD_LOGIC;
50  rd_en : IN STD_LOGIC;
51  dout : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
52  full : OUT STD_LOGIC;
53  overflow : OUT STD_LOGIC;
54  empty : OUT STD_LOGIC;
55  rd_data_count : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
56  wr_data_count : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
57  );
58 END fifo_adc;
59 
60 ARCHITECTURE fifo_adc_a OF fifo_adc IS
61 -- synthesis translate_off
62 COMPONENT wrapped_fifo_adc
63  PORT (
64  rst : IN STD_LOGIC;
65  wr_clk : IN STD_LOGIC;
66  rd_clk : IN STD_LOGIC;
67  din : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
68  wr_en : IN STD_LOGIC;
69  rd_en : IN STD_LOGIC;
70  dout : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
71  full : OUT STD_LOGIC;
72  overflow : OUT STD_LOGIC;
73  empty : OUT STD_LOGIC;
74  rd_data_count : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
75  wr_data_count : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
76  );
77 END COMPONENT;
78 
79 -- Configuration specification
80  FOR ALL : wrapped_fifo_adc USE ENTITY XilinxCoreLib.fifo_generator_v9_3(behavioral)
81  GENERIC MAP (
82  c_add_ngc_constraint => 0,
83  c_application_type_axis => 0,
84  c_application_type_rach => 0,
85  c_application_type_rdch => 0,
86  c_application_type_wach => 0,
87  c_application_type_wdch => 0,
88  c_application_type_wrch => 0,
89  c_axi_addr_width => 32,
90  c_axi_aruser_width => 1,
91  c_axi_awuser_width => 1,
92  c_axi_buser_width => 1,
93  c_axi_data_width => 64,
94  c_axi_id_width => 4,
95  c_axi_ruser_width => 1,
96  c_axi_type => 0,
97  c_axi_wuser_width => 1,
98  c_axis_tdata_width => 64,
99  c_axis_tdest_width => 4,
100  c_axis_tid_width => 8,
101  c_axis_tkeep_width => 4,
102  c_axis_tstrb_width => 4,
103  c_axis_tuser_width => 4,
104  c_axis_type => 0,
105  c_common_clock => 0,
106  c_count_type => 0,
107  c_data_count_width => 10,
108  c_default_value => "BlankString",
109  c_din_width => 16,
110  c_din_width_axis => 1,
111  c_din_width_rach => 32,
112  c_din_width_rdch => 64,
113  c_din_width_wach => 32,
114  c_din_width_wdch => 64,
115  c_din_width_wrch => 2,
116  c_dout_rst_val => "0",
117  c_dout_width => 64,
118  c_enable_rlocs => 0,
119  c_enable_rst_sync => 1,
120  c_error_injection_type => 0,
121  c_error_injection_type_axis => 0,
122  c_error_injection_type_rach => 0,
123  c_error_injection_type_rdch => 0,
124  c_error_injection_type_wach => 0,
125  c_error_injection_type_wdch => 0,
126  c_error_injection_type_wrch => 0,
127  c_family => "virtex4",
128  c_full_flags_rst_val => 1,
129  c_has_almost_empty => 0,
130  c_has_almost_full => 0,
131  c_has_axi_aruser => 0,
132  c_has_axi_awuser => 0,
133  c_has_axi_buser => 0,
134  c_has_axi_rd_channel => 0,
135  c_has_axi_ruser => 0,
136  c_has_axi_wr_channel => 0,
137  c_has_axi_wuser => 0,
138  c_has_axis_tdata => 0,
139  c_has_axis_tdest => 0,
140  c_has_axis_tid => 0,
141  c_has_axis_tkeep => 0,
142  c_has_axis_tlast => 0,
143  c_has_axis_tready => 1,
144  c_has_axis_tstrb => 0,
145  c_has_axis_tuser => 0,
146  c_has_backup => 0,
147  c_has_data_count => 0,
148  c_has_data_counts_axis => 0,
149  c_has_data_counts_rach => 0,
150  c_has_data_counts_rdch => 0,
151  c_has_data_counts_wach => 0,
152  c_has_data_counts_wdch => 0,
153  c_has_data_counts_wrch => 0,
154  c_has_int_clk => 0,
155  c_has_master_ce => 0,
156  c_has_meminit_file => 0,
157  c_has_overflow => 1,
158  c_has_prog_flags_axis => 0,
159  c_has_prog_flags_rach => 0,
160  c_has_prog_flags_rdch => 0,
161  c_has_prog_flags_wach => 0,
162  c_has_prog_flags_wdch => 0,
163  c_has_prog_flags_wrch => 0,
164  c_has_rd_data_count => 1,
165  c_has_rd_rst => 0,
166  c_has_rst => 1,
167  c_has_slave_ce => 0,
168  c_has_srst => 0,
169  c_has_underflow => 0,
170  c_has_valid => 0,
171  c_has_wr_ack => 0,
172  c_has_wr_data_count => 1,
173  c_has_wr_rst => 0,
174  c_implementation_type => 2,
175  c_implementation_type_axis => 1,
176  c_implementation_type_rach => 1,
177  c_implementation_type_rdch => 1,
178  c_implementation_type_wach => 1,
179  c_implementation_type_wdch => 1,
180  c_implementation_type_wrch => 1,
181  c_init_wr_pntr_val => 0,
182  c_interface_type => 0,
183  c_memory_type => 1,
184  c_mif_file_name => "BlankString",
185  c_msgon_val => 1,
186  c_optimization_mode => 0,
187  c_overflow_low => 0,
188  c_preload_latency => 1,
189  c_preload_regs => 0,
190  c_prim_fifo_type => "1kx18",
191  c_prog_empty_thresh_assert_val => 2,
192  c_prog_empty_thresh_assert_val_axis => 1022,
193  c_prog_empty_thresh_assert_val_rach => 1022,
194  c_prog_empty_thresh_assert_val_rdch => 1022,
195  c_prog_empty_thresh_assert_val_wach => 1022,
196  c_prog_empty_thresh_assert_val_wdch => 1022,
197  c_prog_empty_thresh_assert_val_wrch => 1022,
198  c_prog_empty_thresh_negate_val => 3,
199  c_prog_empty_type => 0,
200  c_prog_empty_type_axis => 0,
201  c_prog_empty_type_rach => 0,
202  c_prog_empty_type_rdch => 0,
203  c_prog_empty_type_wach => 0,
204  c_prog_empty_type_wdch => 0,
205  c_prog_empty_type_wrch => 0,
206  c_prog_full_thresh_assert_val => 1021,
207  c_prog_full_thresh_assert_val_axis => 1023,
208  c_prog_full_thresh_assert_val_rach => 1023,
209  c_prog_full_thresh_assert_val_rdch => 1023,
210  c_prog_full_thresh_assert_val_wach => 1023,
211  c_prog_full_thresh_assert_val_wdch => 1023,
212  c_prog_full_thresh_assert_val_wrch => 1023,
213  c_prog_full_thresh_negate_val => 1020,
214  c_prog_full_type => 0,
215  c_prog_full_type_axis => 0,
216  c_prog_full_type_rach => 0,
217  c_prog_full_type_rdch => 0,
218  c_prog_full_type_wach => 0,
219  c_prog_full_type_wdch => 0,
220  c_prog_full_type_wrch => 0,
221  c_rach_type => 0,
222  c_rd_data_count_width => 8,
223  c_rd_depth => 256,
224  c_rd_freq => 1,
225  c_rd_pntr_width => 8,
226  c_rdch_type => 0,
227  c_reg_slice_mode_axis => 0,
228  c_reg_slice_mode_rach => 0,
229  c_reg_slice_mode_rdch => 0,
230  c_reg_slice_mode_wach => 0,
231  c_reg_slice_mode_wdch => 0,
232  c_reg_slice_mode_wrch => 0,
233  c_synchronizer_stage => 2,
234  c_underflow_low => 0,
235  c_use_common_overflow => 0,
236  c_use_common_underflow => 0,
237  c_use_default_settings => 0,
238  c_use_dout_rst => 1,
239  c_use_ecc => 0,
240  c_use_ecc_axis => 0,
241  c_use_ecc_rach => 0,
242  c_use_ecc_rdch => 0,
243  c_use_ecc_wach => 0,
244  c_use_ecc_wdch => 0,
245  c_use_ecc_wrch => 0,
246  c_use_embedded_reg => 0,
247  c_use_fifo16_flags => 0,
248  c_use_fwft_data_count => 0,
249  c_valid_low => 0,
250  c_wach_type => 0,
251  c_wdch_type => 0,
252  c_wr_ack_low => 0,
253  c_wr_data_count_width => 10,
254  c_wr_depth => 1024,
255  c_wr_depth_axis => 1024,
256  c_wr_depth_rach => 16,
257  c_wr_depth_rdch => 1024,
258  c_wr_depth_wach => 16,
259  c_wr_depth_wdch => 1024,
260  c_wr_depth_wrch => 16,
261  c_wr_freq => 1,
262  c_wr_pntr_width => 10,
263  c_wr_pntr_width_axis => 10,
264  c_wr_pntr_width_rach => 4,
265  c_wr_pntr_width_rdch => 10,
266  c_wr_pntr_width_wach => 4,
267  c_wr_pntr_width_wdch => 10,
268  c_wr_pntr_width_wrch => 4,
269  c_wr_response_latency => 1,
270  c_wrch_type => 0
271  );
272 -- synthesis translate_on
273 BEGIN
274 -- synthesis translate_off
275 U0 : wrapped_fifo_adc
276  PORT MAP (
277  rst => rst,
278  wr_clk => wr_clk,
279  rd_clk => rd_clk,
280  din => din,
281  wr_en => wr_en,
282  rd_en => rd_en,
283  dout => dout,
284  full => full,
285  overflow => overflow,
286  empty => empty,
287  rd_data_count => rd_data_count,
288  wr_data_count => wr_data_count
289  );
290 -- synthesis translate_on
291 
292 END fifo_adc_a;
fifo_adc
Definition: fifo_adc.vhd:43