otsdaq_prepmodernization  v2_05_02_indev
EthernetRAM_prod.vhd
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9 --------------------------------------------------------------------------------
10 --
11 -- BLK MEM GEN v7.1 Core - Top-level wrapper
12 --
13 --------------------------------------------------------------------------------
14 --
15 -- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
16 --
17 -- This file contains confidential and proprietary information
18 -- of Xilinx, Inc. and is protected under U.S. and
19 -- international copyright and other intellectual property
20 -- laws.
21 --
22 -- DISCLAIMER
23 -- This disclaimer is not a license and does not grant any
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25 -- otherwise provided in a valid license issued to you by
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29 -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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43 --
44 -- CRITICAL APPLICATIONS
45 -- Xilinx products are not designed or intended to be fail-
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52 -- (individually and collectively, "Critical
53 -- Applications"). Customer assumes the sole risk and
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57 --
58 -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
59 -- PART OF THIS FILE AT ALL TIMES.
60 --
61 --------------------------------------------------------------------------------
62 --
63 -- Filename: EthernetRAM_prod.vhd
64 --
65 -- Description:
66 -- This is the top-level BMG wrapper (over BMG core).
67 --
68 --------------------------------------------------------------------------------
69 -- Author: IP Solutions Division
70 --
71 -- History: August 31, 2005 - First Release
72 --------------------------------------------------------------------------------
73 --
74 -- Configured Core Parameter Values:
75 -- (Refer to the SIM Parameters table in the datasheet for more information on
76 -- the these parameters.)
77 -- C_FAMILY : virtex4
78 -- C_XDEVICEFAMILY : virtex4
79 -- C_INTERFACE_TYPE : 0
80 -- C_ENABLE_32BIT_ADDRESS : 0
81 -- C_AXI_TYPE : 1
82 -- C_AXI_SLAVE_TYPE : 0
83 -- C_AXI_ID_WIDTH : 4
84 -- C_MEM_TYPE : 0
85 -- C_BYTE_SIZE : 9
86 -- C_ALGORITHM : 1
87 -- C_PRIM_TYPE : 1
88 -- C_LOAD_INIT_FILE : 0
89 -- C_INIT_FILE_NAME : no_coe_file_loaded
90 -- C_USE_DEFAULT_DATA : 0
91 -- C_DEFAULT_DATA : 0
92 -- C_RST_TYPE : SYNC
93 -- C_HAS_RSTA : 0
94 -- C_RST_PRIORITY_A : CE
95 -- C_RSTRAM_A : 0
96 -- C_INITA_VAL : 0
97 -- C_HAS_ENA : 0
98 -- C_HAS_REGCEA : 0
99 -- C_USE_BYTE_WEA : 0
100 -- C_WEA_WIDTH : 1
101 -- C_WRITE_MODE_A : READ_FIRST
102 -- C_WRITE_WIDTH_A : 64
103 -- C_READ_WIDTH_A : 64
104 -- C_WRITE_DEPTH_A : 1024
105 -- C_READ_DEPTH_A : 1024
106 -- C_ADDRA_WIDTH : 10
107 -- C_HAS_RSTB : 0
108 -- C_RST_PRIORITY_B : CE
109 -- C_RSTRAM_B : 0
110 -- C_INITB_VAL : 0
111 -- C_HAS_ENB : 0
112 -- C_HAS_REGCEB : 0
113 -- C_USE_BYTE_WEB : 0
114 -- C_WEB_WIDTH : 1
115 -- C_WRITE_MODE_B : WRITE_FIRST
116 -- C_WRITE_WIDTH_B : 64
117 -- C_READ_WIDTH_B : 64
118 -- C_WRITE_DEPTH_B : 1024
119 -- C_READ_DEPTH_B : 1024
120 -- C_ADDRB_WIDTH : 10
121 -- C_HAS_MEM_OUTPUT_REGS_A : 0
122 -- C_HAS_MEM_OUTPUT_REGS_B : 0
123 -- C_HAS_MUX_OUTPUT_REGS_A : 0
124 -- C_HAS_MUX_OUTPUT_REGS_B : 0
125 -- C_HAS_SOFTECC_INPUT_REGS_A : 0
126 -- C_HAS_SOFTECC_OUTPUT_REGS_B : 0
127 -- C_MUX_PIPELINE_STAGES : 0
128 -- C_USE_ECC : 0
129 -- C_USE_SOFTECC : 0
130 -- C_HAS_INJECTERR : 0
131 -- C_SIM_COLLISION_CHECK : ALL
132 -- C_COMMON_CLK : 0
133 -- C_DISABLE_WARN_BHV_COLL : 0
134 -- C_DISABLE_WARN_BHV_RANGE : 0
135 
136 --------------------------------------------------------------------------------
137 -- Library Declarations
138 --------------------------------------------------------------------------------
139 
140 LIBRARY IEEE;
141 USE IEEE.STD_LOGIC_1164.ALL;
142 USE IEEE.STD_LOGIC_ARITH.ALL;
143 USE IEEE.STD_LOGIC_UNSIGNED.ALL;
144 
145 LIBRARY UNISIM;
146 USE UNISIM.VCOMPONENTS.ALL;
147 
148 --------------------------------------------------------------------------------
149 -- Entity Declaration
150 --------------------------------------------------------------------------------
151 ENTITY EthernetRAM_prod IS
152  PORT (
153  --Port A
154  CLKA : IN STD_LOGIC;
155  RSTA : IN STD_LOGIC; --opt port
156  ENA : IN STD_LOGIC; --optional port
157  REGCEA : IN STD_LOGIC; --optional port
158  WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
159  ADDRA : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
160  DINA : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
161  DOUTA : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
162 
163  --Port B
164  CLKB : IN STD_LOGIC;
165  RSTB : IN STD_LOGIC; --opt port
166  ENB : IN STD_LOGIC; --optional port
167  REGCEB : IN STD_LOGIC; --optional port
168  WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
169  ADDRB : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
170  DINB : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
171  DOUTB : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
172 
173  --ECC
174  INJECTSBITERR : IN STD_LOGIC; --optional port
175  INJECTDBITERR : IN STD_LOGIC; --optional port
176  SBITERR : OUT STD_LOGIC; --optional port
177  DBITERR : OUT STD_LOGIC; --optional port
178  RDADDRECC : OUT STD_LOGIC_VECTOR(9 DOWNTO 0); --optional port
179  -- AXI BMG Input and Output Port Declarations
180 
181  -- AXI Global Signals
182  S_ACLK : IN STD_LOGIC;
183  S_AXI_AWID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
184  S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
185  S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
186  S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
187  S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
188  S_AXI_AWVALID : IN STD_LOGIC;
189  S_AXI_AWREADY : OUT STD_LOGIC;
190  S_AXI_WDATA : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
191  S_AXI_WSTRB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
192  S_AXI_WLAST : IN STD_LOGIC;
193  S_AXI_WVALID : IN STD_LOGIC;
194  S_AXI_WREADY : OUT STD_LOGIC;
195  S_AXI_BID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
196  S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
197  S_AXI_BVALID : OUT STD_LOGIC;
198  S_AXI_BREADY : IN STD_LOGIC;
199 
200  -- AXI Full/Lite Slave Read (Write side)
201  S_AXI_ARID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
202  S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
203  S_AXI_ARLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
204  S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
205  S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
206  S_AXI_ARVALID : IN STD_LOGIC;
207  S_AXI_ARREADY : OUT STD_LOGIC;
208  S_AXI_RID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
209  S_AXI_RDATA : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
210  S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
211  S_AXI_RLAST : OUT STD_LOGIC;
212  S_AXI_RVALID : OUT STD_LOGIC;
213  S_AXI_RREADY : IN STD_LOGIC;
214 
215  -- AXI Full/Lite Sideband Signals
216  S_AXI_INJECTSBITERR : IN STD_LOGIC;
217  S_AXI_INJECTDBITERR : IN STD_LOGIC;
218  S_AXI_SBITERR : OUT STD_LOGIC;
219  S_AXI_DBITERR : OUT STD_LOGIC;
220  S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
221  S_ARESETN : IN STD_LOGIC
222 
223 
224  );
225 
226 END EthernetRAM_prod;
227 
228 
229 ARCHITECTURE xilinx OF EthernetRAM_prod IS
230 
231  COMPONENT EthernetRAM_exdes IS
232  PORT (
233  --Port A
234 
235  WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
236  ADDRA : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
237 
238  DINA : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
239 
240  DOUTA : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
241 
242  CLKA : IN STD_LOGIC
243 
244 
245 
246 
247  );
248  END COMPONENT;
249 
250 BEGIN
251 
252  bmg0 : EthernetRAM_exdes
253  PORT MAP (
254  --Port A
255 
256  WEA => WEA,
257  ADDRA => ADDRA,
258 
259  DINA => DINA,
260 
261  DOUTA => DOUTA,
262 
263  CLKA => CLKA
264 
265 
266 
267  );
268 END xilinx;
EthernetRAM_exdes
Definition: EthernetRAM_exdes.vhd:88
EthernetRAM_prod
Definition: EthernetRAM_prod.vhd:151