otsdaq_prepmodernization  v2_05_02_indev
EthernetRAM_exdes.vhd
1 
2 
3 
4 
5 
6 
7 
8 --------------------------------------------------------------------------------
9 --
10 -- BLK MEM GEN v7.1 Core - Top-level core wrapper
11 --
12 --------------------------------------------------------------------------------
13 --
14 -- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved.
15 --
16 -- This file contains confidential and proprietary information
17 -- of Xilinx, Inc. and is protected under U.S. and
18 -- international copyright and other intellectual property
19 -- laws.
20 --
21 -- DISCLAIMER
22 -- This disclaimer is not a license and does not grant any
23 -- rights to the materials distributed herewith. Except as
24 -- otherwise provided in a valid license issued to you by
25 -- Xilinx, and to the maximum extent permitted by applicable
26 -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
27 -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
28 -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
29 -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
30 -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
31 -- (2) Xilinx shall not be liable (whether in contract or tort,
32 -- including negligence, or under any other theory of
33 -- liability) for any loss or damage of any kind or nature
34 -- related to, arising under or in connection with these
35 -- materials, including for any direct, or any indirect,
36 -- special, incidental, or consequential loss or damage
37 -- (including loss of data, profits, goodwill, or any type of
38 -- loss or damage suffered as a result of any action brought
39 -- by a third party) even if such damage or loss was
40 -- reasonably foreseeable or Xilinx had been advised of the
41 -- possibility of the same.
42 --
43 -- CRITICAL APPLICATIONS
44 -- Xilinx products are not designed or intended to be fail-
45 -- safe, or for use in any application requiring fail-safe
46 -- performance, such as life-support or safety devices or
47 -- systems, Class III medical devices, nuclear facilities,
48 -- applications related to the deployment of airbags, or any
49 -- other applications that could lead to death, personal
50 -- injury, or severe property or environmental damage
51 -- (individually and collectively, "Critical
52 -- Applications"). Customer assumes the sole risk and
53 -- liability of any use of Xilinx products in Critical
54 -- Applications, subject only to applicable laws and
55 -- regulations governing limitations on product liability.
56 --
57 -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
58 -- PART OF THIS FILE AT ALL TIMES.
59 
60 --------------------------------------------------------------------------------
61 --
62 -- Filename: EthernetRAM_exdes.vhd
63 --
64 -- Description:
65 -- This is the actual BMG core wrapper.
66 --
67 --------------------------------------------------------------------------------
68 -- Author: IP Solutions Division
69 --
70 -- History: August 31, 2005 - First Release
71 --------------------------------------------------------------------------------
72 --
73 --------------------------------------------------------------------------------
74 -- Library Declarations
75 --------------------------------------------------------------------------------
76 
77 LIBRARY IEEE;
78 USE IEEE.STD_LOGIC_1164.ALL;
79 USE IEEE.STD_LOGIC_ARITH.ALL;
80 USE IEEE.STD_LOGIC_UNSIGNED.ALL;
81 
82 LIBRARY UNISIM;
83 USE UNISIM.VCOMPONENTS.ALL;
84 
85 --------------------------------------------------------------------------------
86 -- Entity Declaration
87 --------------------------------------------------------------------------------
88 ENTITY EthernetRAM_exdes IS
89  PORT (
90  --Inputs - Port A
91 
92  WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
93  ADDRA : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
94 
95  DINA : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
96 
97  DOUTA : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
98  CLKA : IN STD_LOGIC
99 
100 
101  );
102 
103 END EthernetRAM_exdes;
104 
105 
106 ARCHITECTURE xilinx OF EthernetRAM_exdes IS
107 
108  COMPONENT BUFG IS
109  PORT (
110  I : IN STD_ULOGIC;
111  O : OUT STD_ULOGIC
112  );
113  END COMPONENT;
114 
115  COMPONENT EthernetRAM IS
116  PORT (
117  --Port A
118 
119  WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
120  ADDRA : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
121 
122  DINA : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
123 
124  DOUTA : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
125 
126  CLKA : IN STD_LOGIC
127 
128 
129 
130  );
131  END COMPONENT;
132 
133  SIGNAL CLKA_buf : STD_LOGIC;
134  SIGNAL CLKB_buf : STD_LOGIC;
135  SIGNAL S_ACLK_buf : STD_LOGIC;
136 
137 BEGIN
138 
139  bufg_A : BUFG
140  PORT MAP (
141  I => CLKA,
142  O => CLKA_buf
143  );
144 
145 
146 
147  bmg0 : EthernetRAM
148  PORT MAP (
149  --Port A
150 
151  WEA => WEA,
152  ADDRA => ADDRA,
153 
154  DINA => DINA,
155 
156  DOUTA => DOUTA,
157 
158  CLKA => CLKA_buf
159 
160 
161  );
162 
163 END xilinx;
EthernetRAM_exdes
Definition: EthernetRAM_exdes.vhd:88