EthernetRAM_exdes Entity Reference

Libraries
IEEE
UNISIM

Use Clauses
IEEE.STD_LOGIC_1164.all
IEEE.STD_LOGIC_ARITH.all
IEEE.STD_LOGIC_UNSIGNED.all
UNISIM.VCOMPONENTS.all

Ports
WEA	in STD_LOGIC_VECTOR ( 0 downto 0 )
ADDRA	in STD_LOGIC_VECTOR ( 9 downto 0 )
DINA	in STD_LOGIC_VECTOR ( 63 downto 0 )
DOUTA	out STD_LOGIC_VECTOR ( 63 downto 0 )
CLKA	in STD_LOGIC

Detailed Description

Definition at line 88 of file EthernetRAM_exdes.vhd.

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The documentation for this class was generated from the following file:

• otsdaq_prepmodernization/firmware/g-2/KickerControllerFirmware/GEL_CAPTAN/ipcore_dir/EthernetRAM/example_design/EthernetRAM_exdes.vhd