EthernetRAM Entity Reference

Libraries
ieee
XilinxCoreLib

Use Clauses
ieee.std_logic_1164.all

Ports
clka	in STD_LOGIC
wea	in STD_LOGIC_VECTOR ( 0 downto 0 )
addra	in STD_LOGIC_VECTOR ( 9 downto 0 )
dina	in STD_LOGIC_VECTOR ( 63 downto 0 )
douta	out STD_LOGIC_VECTOR ( 63 downto 0 )

Detailed Description

Definition at line 43 of file EthernetRAM.vhd.

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The documentation for this class was generated from the following file:

• otsdaq_prepmodernization/firmware/g-2/KickerControllerFirmware/GEL_CAPTAN/ipcore_dir/EthernetRAM.vhd