otsdaq_prepmodernization  v2_05_02_indev
ethernetFIFO_exdes.vhd
1 --------------------------------------------------------------------------------
2 --
3 -- FIFO Generator Core - core top file for implementation
4 --
5 --------------------------------------------------------------------------------
6 --
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52 --------------------------------------------------------------------------------
53 --
54 -- Filename: ethernetFIFO_exdes.vhd
55 --
56 -- Description:
57 -- This is the FIFO core wrapper with BUFG instances for clock connections.
58 --
59 --------------------------------------------------------------------------------
60 -- Library Declarations
61 --------------------------------------------------------------------------------
62 
63 library ieee;
64 use ieee.std_logic_1164.all;
65 use ieee.std_logic_arith.all;
66 use ieee.std_logic_unsigned.all;
67 
68 library unisim;
69 use unisim.vcomponents.all;
70 
71 --------------------------------------------------------------------------------
72 -- Entity Declaration
73 --------------------------------------------------------------------------------
74 entity ethernetFIFO_exdes is
75  PORT (
76  WR_CLK : IN std_logic;
77  RD_CLK : IN std_logic;
78  RST : IN std_logic;
79  PROG_EMPTY : OUT std_logic;
80  WR_EN : IN std_logic;
81  RD_EN : IN std_logic;
82  DIN : IN std_logic_vector(32-1 DOWNTO 0);
83  DOUT : OUT std_logic_vector(128-1 DOWNTO 0);
84  FULL : OUT std_logic;
85  EMPTY : OUT std_logic);
86 
87 end ethernetFIFO_exdes;
88 
89 
90 
91 architecture xilinx of ethernetFIFO_exdes is
92 
93  signal wr_clk_i : std_logic;
94  signal rd_clk_i : std_logic;
95 
96 
97 
98  component ethernetFIFO is
99  PORT (
100  WR_CLK : IN std_logic;
101  RD_CLK : IN std_logic;
102  RST : IN std_logic;
103  PROG_EMPTY : OUT std_logic;
104  WR_EN : IN std_logic;
105  RD_EN : IN std_logic;
106  DIN : IN std_logic_vector(32-1 DOWNTO 0);
107  DOUT : OUT std_logic_vector(128-1 DOWNTO 0);
108  FULL : OUT std_logic;
109  EMPTY : OUT std_logic);
110 
111  end component;
112 
113 
114 begin
115 
116  wr_clk_buf: bufg
117  PORT map(
118  i => WR_CLK,
119  o => wr_clk_i
120  );
121 
122  rd_clk_buf: bufg
123  PORT map(
124  i => RD_CLK,
125  o => rd_clk_i
126  );
127 
128 
129  exdes_inst : ethernetFIFO
130  PORT MAP (
131  WR_CLK => wr_clk_i,
132  RD_CLK => rd_clk_i,
133  RST => rst,
134  PROG_EMPTY => prog_empty,
135  WR_EN => wr_en,
136  RD_EN => rd_en,
137  DIN => din,
138  DOUT => dout,
139  FULL => full,
140  EMPTY => empty);
141 
142 end xilinx;
ethernetFIFO_exdes
Definition: ethernetFIFO_exdes.vhd:74