otsdaq_prepmodernization  v2_05_02_indev
ethernetFIFO Entity Reference

Libraries

ieee 
XilinxCoreLib 

Use Clauses

ieee.std_logic_1164.all 

Ports

rst   in STD_LOGIC
wr_clk   in STD_LOGIC
rd_clk   in STD_LOGIC
din   in STD_LOGIC_VECTOR ( 31 downto 0 )
wr_en   in STD_LOGIC
rd_en   in STD_LOGIC
dout   out STD_LOGIC_VECTOR ( 127 downto 0 )
full   out STD_LOGIC
empty   out STD_LOGIC
prog_empty   out STD_LOGIC

Detailed Description

Definition at line 43 of file ethernetFIFO.vhd.


The documentation for this class was generated from the following file: