otsdaq_prepmodernization
v2_05_02_indev
|
Libraries | |
IEEE |
Use Clauses | |
IEEE.STD_LOGIC_1164.all | |
IEEE.NUMERIC_STD.all | |
IEEE.STD_LOGIC_UNSIGNED.all |
Ports | |
clk | in STD_LOGIC |
reset | in STD_LOGIC |
clock_enable | in STD_LOGIC |
data_in | in STD_LOGIC_VECTOR ( 63 downto 0 ) |
data_in_we | in STD_LOGIC |
data_in_end | in STD_LOGIC |
footer_in | STD_LOGIC_VECTOR ( 63 downto 0 ) |
zero_cross_thresh_high | in STD_LOGIC_VECTOR ( 7 downto 0 ) |
zero_cross_thresh_low | in STD_LOGIC_VECTOR ( 7 downto 0 ) |
zero_cross_veto_thresh | in STD_LOGIC_VECTOR ( 7 downto 0 ) |
clear_veto | in STD_LOGIC |
force_veto | in STD_LOGIC |
veto_en | in STD_LOGIC |
data_out | out STD_LOGIC_VECTOR ( 63 downto 0 ) |
data_out_we | out STD_LOGIC |
data_out_end | out STD_LOGIC |
zero_cross_count | out STD_LOGIC_VECTOR ( 7 downto 0 ) |
veto | out STD_LOGIC |
reset_clear_veto | out STD_LOGIC |
reset_force_veto | out STD_LOGIC |
Definition at line 37 of file event_analysis.vhd.