otsdaq_prepmodernization  v2_05_02_indev
buf_one_exdes Entity Reference

Libraries

IEEE 
UNISIM 

Use Clauses

IEEE.STD_LOGIC_1164.all 
IEEE.STD_LOGIC_ARITH.all 
IEEE.STD_LOGIC_UNSIGNED.all 
UNISIM.VCOMPONENTS.all 

Ports

WEA   in STD_LOGIC_VECTOR ( 0 downto 0 )
ADDRA   in STD_LOGIC_VECTOR ( 9 downto 0 )
DINA   in STD_LOGIC_VECTOR ( 31 downto 0 )
CLKA   in STD_LOGIC
ADDRB   in STD_LOGIC_VECTOR ( 9 downto 0 )
DOUTB   out STD_LOGIC_VECTOR ( 31 downto 0 )
CLKB   in STD_LOGIC

Detailed Description

Definition at line 88 of file buf_one_exdes.vhd.


The documentation for this class was generated from the following file: