buf_one_exdes.vhd

 
 
 




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--
-- BLK MEM GEN v7.1 Core - Top-level core wrapper
--
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--
-- Filename: buf_one_exdes.vhd
--
-- Description:
--   This is the actual BMG core wrapper.
--
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-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
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--
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-- Library Declarations
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LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;

--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY buf_one_exdes IS
  PORT (
      --Inputs - Port A
  
    WEA            : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
    ADDRA          : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
  
    DINA           : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
  
    CLKA       : IN STD_LOGIC;

  
      --Inputs - Port B
    ADDRB          : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
    DOUTB          : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
    CLKB           : IN STD_LOGIC

  );

END buf_one_exdes;


ARCHITECTURE xilinx OF buf_one_exdes IS

  COMPONENT BUFG IS
  PORT (
     I      : IN STD_ULOGIC;
     O      : OUT STD_ULOGIC
  );
  END COMPONENT;

  COMPONENT buf_one IS
  PORT (
      --Port A
  
    WEA        : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
    ADDRA      : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
  
    DINA       : IN STD_LOGIC_VECTOR(31 DOWNTO 0);

  
    CLKA       : IN STD_LOGIC;

  
      --Port B
    ADDRB      : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
    DOUTB      : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
    CLKB       : IN STD_LOGIC


  );
  END COMPONENT;

  SIGNAL CLKA_buf     : STD_LOGIC;
  SIGNAL CLKB_buf     : STD_LOGIC;
  SIGNAL S_ACLK_buf   : STD_LOGIC;

BEGIN

  bufg_A : BUFG
    PORT MAP (
     I  => CLKA,
     O  => CLKA_buf 
     );

  bufg_B : BUFG
    PORT MAP (
     I  => CLKB,
     O  => CLKB_buf 
     );


  bmg0 : buf_one
    PORT MAP (
      --Port A
  
      WEA         => WEA,
      ADDRA       => ADDRA,
  
      DINA        => DINA,

      CLKA        => CLKA_buf ,

  
      --Port B
      ADDRB       => ADDRB,
      DOUTB       => DOUTB,
      CLKB        => CLKB_buf 

    );

END xilinx;