blk_mem_gen_v2_6 Entity Reference

Libraries
ieee
UNISIM

Use Clauses
ieee.std_logic_1164.all
ieee.numeric_std.all
UNISIM.Vcomponents.all

Ports
addra	in std_logic_vector ( 5 downto 0 )
addrb	in std_logic_vector ( 5 downto 0 )
clka	in std_logic
clkb	in std_logic
dina	in std_logic_vector ( 63 downto 0 )
dinb	in std_logic_vector ( 63 downto 0 )
wea	in std_logic_vector ( 0 downto 0 )
web	in std_logic_vector ( 0 downto 0 )
douta	out std_logic_vector ( 63 downto 0 )
doutb	out std_logic_vector ( 63 downto 0 )

Detailed Description

Definition at line 24 of file blk_mem_gen_v2_6.vhd.

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The documentation for this class was generated from the following file:

• otsdaq_prepmodernization/firmware/g-2/KickerControllerFirmware/GEL_CAPTAN/blk_mem_gen_v2_6.vhd