Ethernet_RAM_exdes Entity Reference

Libraries
ieee
unisim

Use Clauses
ieee.std_logic_1164.all
ieee.std_logic_arith.all
ieee.std_logic_unsigned.all
unisim.vcomponents.all

Ports
CLK	in STD_LOGIC := ' 0 '
WE	in STD_LOGIC := ' 0 '
SPO	out STD_LOGIC_VECTOR ( 64 - 1 downto 0 )
A	in STD_LOGIC_VECTOR ( 11 - 1 - ( 4 * 0 * boolean ' pos ) downto 0 ) := ( others = > ' 0 ' )
D	in STD_LOGIC_VECTOR ( 64 - 1 downto 0 ) := ( others = > ' 0 ' )
DPRA	in STD_LOGIC_VECTOR ( 11 - 1 downto 0 ) := ( others = > ' 0 ' )
SPRA	in STD_LOGIC_VECTOR ( 11 - 1 downto 0 ) := ( others = > ' 0 ' )
I_CE	in STD_LOGIC := ' 1 '
QSPO_CE	in STD_LOGIC := ' 1 '
QDPO_CE	in STD_LOGIC := ' 1 '
QDPO_CLK	in STD_LOGIC := ' 0 '
QSPO_RST	in STD_LOGIC := ' 0 '
QDPO_RST	in STD_LOGIC := ' 0 '
QSPO_SRST	in STD_LOGIC := ' 0 '
QDPO_SRST	in STD_LOGIC := ' 0 '
DPO	out STD_LOGIC_VECTOR ( 64 - 1 downto 0 )
QSPO	out STD_LOGIC_VECTOR ( 64 - 1 downto 0 )
QDPO	out STD_LOGIC_VECTOR ( 64 - 1 downto 0 )

Detailed Description

Definition at line 76 of file Ethernet_RAM_exdes.vhd.

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The documentation for this class was generated from the following files:

• otsdaq_prepmodernization/firmware/g-2/KickerControllerFirmware/GEL_CAPTAN/ipcore_dir/Ethernet_RAM/example_design/Ethernet_RAM_exdes.vhd
• otsdaq_prepmodernization/firmware/g-2/KickerControllerFirmware/GEL_CAPTAN/ipcore_dir/Ethernet_RAM/example_design/Ethernet_RAM_prod_exdes.vhd