ADC_FIFO_exdes Entity Reference

Libraries
ieee
unisim

Use Clauses
ieee.std_logic_1164.all
ieee.std_logic_arith.all
ieee.std_logic_unsigned.all
unisim.vcomponents.all

Ports
WR_CLK	in std_logic
RD_CLK	in std_logic
VALID	out std_logic
OVERFLOW	out std_logic
WR_EN	in std_logic
RD_EN	in std_logic
DIN	in std_logic_vector ( 16 - 1 downto 0 )
DOUT	out std_logic_vector ( 64 - 1 downto 0 )
FULL	out std_logic
EMPTY	out std_logic

Detailed Description

Definition at line 74 of file ADC_FIFO_exdes.vhd.

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The documentation for this class was generated from the following file:

• otsdaq_prepmodernization/firmware/g-2/KickerControllerFirmware/GEL_CAPTAN/ipcore_dir/ADC_FIFO/example_design/ADC_FIFO_exdes.vhd