2 --------------------------------------------------------------------------------
4 -- BLK MEM GEN v7_3 Core - Data Generator
6 --------------------------------------------------------------------------------
8 -- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
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30 -- special, incidental, or consequential loss or damage
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54 --------------------------------------------------------------------------------
56 -- Filename: data_gen.vhd
61 --------------------------------------------------------------------------------
62 -- Author: IP Solutions Division
64 -- History: Sep 12, 2011 - First Release
65 --------------------------------------------------------------------------------
67 --------------------------------------------------------------------------------
68 -- Library Declarations
69 --------------------------------------------------------------------------------
72 USE IEEE.STD_LOGIC_1164.
ALL;
73 USE IEEE.STD_LOGIC_ARITH.
ALL;
74 USE IEEE.STD_LOGIC_UNSIGNED.
ALL;
77 USE work.BMG_TB_PKG.
ALL;
80 GENERIC ( DATA_GEN_WIDTH : := 32;
90 DATA_OUT : OUT (DOUT_WIDTH-1 DOWNTO 0) --OUTPUT VECTOR
94 ARCHITECTURE DATA_GEN_ARCH
OF DATA_GEN IS
95 CONSTANT LOOP_COUNT : := DIVROUNDUP(DATA_GEN_WIDTH,8);
96 SIGNAL RAND_DATA : (8*LOOP_COUNT-1 DOWNTO 0);
97 SIGNAL LOCAL_DATA_OUT : (DATA_GEN_WIDTH-1 DOWNTO 0);
98 SIGNAL LOCAL_CNT : :=1;
99 SIGNAL DATA_GEN_I : :='0';
102 LOCAL_DATA_OUT <= RAND_DATA(DATA_GEN_WIDTH-1
DOWNTO 0);
103 DATA_OUT <= LOCAL_DATA_OUT(((DOUT_WIDTH*LOCAL_CNT)-1) DOWNTO ((DOUT_WIDTH*LOCAL_CNT)-DOUT_WIDTH));
104 DATA_GEN_I <= '0' WHEN (LOCAL_CNT < DATA_PART_CNT) ELSE EN;
108 IF(RISING_EDGE (CLK)) THEN
109 IF(EN ='1' AND (DATA_PART_CNT =1)) THEN
111 ELSIF(EN='1' AND (DATA_PART_CNT>1)) THEN
112 IF(LOCAL_CNT = 1) THEN
113 LOCAL_CNT <= LOCAL_CNT+1;
114 ELSIF(LOCAL_CNT < DATA_PART_CNT) THEN
115 LOCAL_CNT <= LOCAL_CNT+1;
125 RAND_GEN:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
126 RAND_GEN_INST:
ENTITY work.
RANDOM
135 RANDOM_NUM => RAND_DATA
(8*(N+1
)-
1 DOWNTO 8*N
)
137 END GENERATE RAND_GEN;