otsdaq_prepmodernization  v2_05_02_indev
data_gen.vhd
1 
2 --------------------------------------------------------------------------------
3 --
4 -- BLK MEM GEN v7_3 Core - Data Generator
5 --
6 --------------------------------------------------------------------------------
7 --
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9 --
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53 
54 --------------------------------------------------------------------------------
55 --
56 -- Filename: data_gen.vhd
57 --
58 -- Description:
59 -- Data Generator
60 --
61 --------------------------------------------------------------------------------
62 -- Author: IP Solutions Division
63 --
64 -- History: Sep 12, 2011 - First Release
65 --------------------------------------------------------------------------------
66 --
67 --------------------------------------------------------------------------------
68 -- Library Declarations
69 --------------------------------------------------------------------------------
70 
71 LIBRARY IEEE;
72 USE IEEE.STD_LOGIC_1164.ALL;
73 USE IEEE.STD_LOGIC_ARITH.ALL;
74 USE IEEE.STD_LOGIC_UNSIGNED.ALL;
75 
76 LIBRARY work;
77 USE work.BMG_TB_PKG.ALL;
78 
79 ENTITY DATA_GEN IS
80  GENERIC ( DATA_GEN_WIDTH : INTEGER := 32;
81  DOUT_WIDTH : INTEGER := 32;
82  DATA_PART_CNT : INTEGER := 1;
83  SEED : INTEGER := 2
84  );
85 
86  PORT (
87  CLK : IN STD_LOGIC;
88  RST : IN STD_LOGIC;
89  EN : IN STD_LOGIC;
90  DATA_OUT : OUT STD_LOGIC_VECTOR (DOUT_WIDTH-1 DOWNTO 0) --OUTPUT VECTOR
91  );
92 END DATA_GEN;
93 
94 ARCHITECTURE DATA_GEN_ARCH OF DATA_GEN IS
95  CONSTANT LOOP_COUNT : INTEGER := DIVROUNDUP(DATA_GEN_WIDTH,8);
96  SIGNAL RAND_DATA : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0);
97  SIGNAL LOCAL_DATA_OUT : STD_LOGIC_VECTOR(DATA_GEN_WIDTH-1 DOWNTO 0);
98  SIGNAL LOCAL_CNT : INTEGER :=1;
99  SIGNAL DATA_GEN_I : STD_LOGIC :='0';
100 BEGIN
101 
102  LOCAL_DATA_OUT <= RAND_DATA(DATA_GEN_WIDTH-1 DOWNTO 0);
103  DATA_OUT <= LOCAL_DATA_OUT(((DOUT_WIDTH*LOCAL_CNT)-1) DOWNTO ((DOUT_WIDTH*LOCAL_CNT)-DOUT_WIDTH));
104  DATA_GEN_I <= '0' WHEN (LOCAL_CNT < DATA_PART_CNT) ELSE EN;
105 
106  PROCESS(CLK)
107  BEGIN
108  IF(RISING_EDGE (CLK)) THEN
109  IF(EN ='1' AND (DATA_PART_CNT =1)) THEN
110  LOCAL_CNT <=1;
111  ELSIF(EN='1' AND (DATA_PART_CNT>1)) THEN
112  IF(LOCAL_CNT = 1) THEN
113  LOCAL_CNT <= LOCAL_CNT+1;
114  ELSIF(LOCAL_CNT < DATA_PART_CNT) THEN
115  LOCAL_CNT <= LOCAL_CNT+1;
116  ELSE
117  LOCAL_CNT <= 1;
118  END IF;
119  ELSE
120  LOCAL_CNT <= 1;
121  END IF;
122  END IF;
123  END PROCESS;
124 
125  RAND_GEN:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
126  RAND_GEN_INST:ENTITY work.RANDOM
127  GENERIC MAP(
128  WIDTH => 8,
129  SEED => (SEED+N)
130  )
131  PORT MAP(
132  CLK => CLK,
133  RST => RST,
134  EN => DATA_GEN_I ,
135  RANDOM_NUM => RAND_DATA(8*(N+1)-1 DOWNTO 8*N)
136  );
137  END GENERATE RAND_GEN;
138 
139 END ARCHITECTURE;
140