Ethernet_RAM_tb_stim_gen.vhd

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--
-- DIST MEM GEN Core - Stimulus Generator For Single Port RAM Configuration
--
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--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
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--
-- Filename: Ethernet_RAM_tb_stim_gen.vhd
--
-- Description:
--  Stimulus Generation For ROM
--
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-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
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--
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-- Library Declarations
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LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;

LIBRARY work;
USE work.ALL;

USE work.Ethernet_RAM_TB_PKG.ALL;


ENTITY REGISTER_LOGIC_SRAM IS
  PORT(
    Q   : OUT STD_LOGIC;
    CLK : IN STD_LOGIC;
    RST : IN STD_LOGIC;
    D   : IN STD_LOGIC
  );
END REGISTER_LOGIC_SRAM;

ARCHITECTURE REGISTER_ARCH OF REGISTER_LOGIC_SRAM IS
  SIGNAL Q_O : STD_LOGIC :='0';
BEGIN
  Q <= Q_O;
  FF_BEH: PROCESS(CLK)
  BEGIN
    IF(RISING_EDGE(CLK)) THEN
      IF(RST ='1') THEN
          Q_O <= '0';
      ELSE
        Q_O <= D;
      END IF;
    END IF;
  END PROCESS;
END REGISTER_ARCH;

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;

LIBRARY work;
USE work.ALL;
USE work.Ethernet_RAM_TB_PKG.ALL;

ENTITY Ethernet_RAM_TB_STIM_GEN IS
  PORT (
    CLK : IN STD_LOGIC;
    RST : IN STD_LOGIC;
    A   : OUT  STD_LOGIC_VECTOR(11-1 downto 0)   := (OTHERS => '0'); 
    D   : OUT  STD_LOGIC_VECTOR(64-1 downto 0)         := (OTHERS => '0');
    WE         : OUT  STD_LOGIC  := '0';
    DATA_IN : IN STD_LOGIC_VECTOR (63 DOWNTO 0);   --OUTPUT VECTOR 
        
    CHECK_DATA : OUT STD_LOGIC:= '0'
          );
END Ethernet_RAM_TB_STIM_GEN;

ARCHITECTURE BEHAVIORAL OF Ethernet_RAM_TB_STIM_GEN IS

  CONSTANT ZERO           : STD_LOGIC_VECTOR(31 DOWNTO 0)                := (OTHERS => '0');
  CONSTANT DATA_PART_CNT_A: INTEGER:=1;
  SIGNAL   WRITE_ADDR     : STD_LOGIC_VECTOR(31 DOWNTO 0)                := (OTHERS => '0');
  SIGNAL   WRITE_ADDR_INT : STD_LOGIC_VECTOR(10 DOWNTO 0)   := (OTHERS => '0');
  SIGNAL   DO_READ_REG    : STD_LOGIC_VECTOR(4 DOWNTO 0)                 :=(OTHERS => '0');
  SIGNAL   READ_ADDR_INT  : STD_LOGIC_VECTOR(10 DOWNTO 0)   := (OTHERS => '0');
  SIGNAL   READ_ADDR      : STD_LOGIC_VECTOR(31 DOWNTO 0)                := (OTHERS => '0');
  SIGNAL   D_INT          : STD_LOGIC_VECTOR(63 DOWNTO 0) := (OTHERS => '0');
  SIGNAL   DO_WRITE       : STD_LOGIC                                    := '0';
  SIGNAL   DO_READ        : STD_LOGIC                                    := '0';
  SIGNAL   COUNT_NO       : INTEGER                                      :=0;
BEGIN
  WRITE_ADDR_INT(10 DOWNTO 0) <= WRITE_ADDR(10 DOWNTO 0);
  READ_ADDR_INT(10 DOWNTO 0)  <= READ_ADDR(10 DOWNTO 0);
  A <= IF_THEN_ELSE(DO_WRITE='1',WRITE_ADDR_INT,READ_ADDR_INT); 
  D <= D_INT;
  CHECK_DATA <= DO_READ;

RD_AGEN_INST:ENTITY work.Ethernet_RAM_TB_AGEN
  GENERIC MAP( 
    C_MAX_DEPTH  => 2048 
  )
  PORT MAP(
    CLK         => CLK,
    RST         => RST,
    EN          => DO_READ ,
    LOAD        => '0',
    LOAD_VALUE  => ZERO,
    ADDR_OUT    => READ_ADDR
  );

WR_AGEN_INST:ENTITY work.Ethernet_RAM_TB_AGEN
  GENERIC MAP(
    C_MAX_DEPTH  => 2048  )
  PORT MAP(
    CLK         => CLK,
     RST         => RST,
     EN          => DO_WRITE,
    LOAD        => '0',
     LOAD_VALUE  => ZERO,
     ADDR_OUT    => WRITE_ADDR 
  );

WR_DGEN_INST:ENTITY work.Ethernet_RAM_TB_DGEN
   GENERIC MAP (
     DATA_GEN_WIDTH  => 64,
     DOUT_WIDTH      => 64,
     DATA_PART_CNT   => DATA_PART_CNT_A,
     SEED            => 2
   )
   PORT MAP (
     CLK       => CLK,
      RST       => RST,
     EN        => DO_WRITE ,
     DATA_OUT  => D_INT           
   );

WR_RD_PROCESS: PROCESS (CLK)
BEGIN
  IF(RISING_EDGE(CLK)) THEN
     IF(RST='1') THEN
        DO_WRITE <= '0';
       DO_READ  <= '0';
       COUNT_NO <=  0 ;
     ELSIF(COUNT_NO < 4) THEN
        DO_WRITE <= '1';
       DO_READ  <= '0';
       COUNT_NO <= COUNT_NO + 1;
     ELSIF(COUNT_NO< 8) THEN
        DO_WRITE <= '0';
       DO_READ  <= '1';
       COUNT_NO <= COUNT_NO + 1;
     ELSIF(COUNT_NO=8) THEN
       DO_WRITE <= '0';
       DO_READ  <= '0';
       COUNT_NO <=  0 ;
     END IF;
  END IF;
END PROCESS;

BEGIN_SHIFT_REG: FOR I IN 0 TO 4 GENERATE
BEGIN
  DFF_RIGHT: IF I=0 GENERATE
  BEGIN
    SHIFT_INST_0: ENTITY work.REGISTER_LOGIC_SRAM
      PORT MAP(
        Q    => DO_READ_REG(0),
        CLK  => CLK,
        RST  => RST,
        D    => DO_READ
      );
  END GENERATE DFF_RIGHT;
  DFF_OTHERS: IF ((I>0) AND (I<=4)) GENERATE
  BEGIN
     SHIFT_INST: ENTITY work.REGISTER_LOGIC_SRAM
       PORT MAP(
          Q    => DO_READ_REG (I),
          CLK  => CLK,
          RST  => RST,
          D    => DO_READ_REG (I-1)
       );
  END GENERATE DFF_OTHERS;
END GENERATE BEGIN_SHIFT_REG;


  WE <= IF_THEN_ELSE(DO_WRITE='1','1','0') ;

END ARCHITECTURE;