otsdaq_prepmodernization  v2_05_02_indev
Ethernet_RAM_tb_agen.vhd
1 
2 --------------------------------------------------------------------------------
3 --
4 -- DIST MEM GEN Core - Address Generator
5 --
6 --------------------------------------------------------------------------------
7 --
8 -- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
9 --
10 -- This file contains confidential and proprietary information
11 -- of Xilinx, Inc. and is protected under U.S. and
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14 --
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53 
54 --------------------------------------------------------------------------------
55 --
56 -- Filename: Ethernet_RAM_tb_agen.vhd
57 --
58 -- Description:
59 -- Address Generator
60 --
61 --------------------------------------------------------------------------------
62 -- Author: IP Solutions Division
63 --
64 -- History: Sep 12, 2011 - First Release
65 --------------------------------------------------------------------------------
66 --
67 --------------------------------------------------------------------------------
68 -- Library Declarations
69 --------------------------------------------------------------------------------
70 
71 LIBRARY IEEE;
72 USE IEEE.STD_LOGIC_1164.ALL;
73 USE IEEE.STD_LOGIC_ARITH.ALL;
74 USE IEEE.STD_LOGIC_UNSIGNED.ALL;
75 
76 LIBRARY work;
77 USE work.ALL;
78 
79 ENTITY Ethernet_RAM_TB_AGEN IS
80  GENERIC (
81  C_MAX_DEPTH : INTEGER := 1024 ;
82  RST_VALUE : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS=> '0');
83  RST_INC : INTEGER := 0);
84  PORT (
85  CLK : IN STD_LOGIC;
86  RST : IN STD_LOGIC;
87  EN : IN STD_LOGIC;
88  LOAD :IN STD_LOGIC;
89  LOAD_VALUE : IN STD_LOGIC_VECTOR (31 DOWNTO 0) := (OTHERS => '0');
90  ADDR_OUT : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) --OUTPUT VECTOR
91  );
92 END Ethernet_RAM_TB_AGEN;
93 
94 ARCHITECTURE BEHAVIORAL OF Ethernet_RAM_TB_AGEN IS
95  SIGNAL ADDR_TEMP : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS =>'0');
96 BEGIN
97  ADDR_OUT <= ADDR_TEMP;
98  PROCESS(CLK)
99  BEGIN
100  IF(RISING_EDGE(CLK)) THEN
101  IF(RST='1') THEN
102  ADDR_TEMP<= RST_VALUE + conv_std_logic_vector(RST_INC,32 );
103  ELSE
104  IF(EN='1') THEN
105  IF(LOAD='1') THEN
106  ADDR_TEMP <=LOAD_VALUE;
107  ELSE
108  IF(ADDR_TEMP = C_MAX_DEPTH-1) THEN
109  ADDR_TEMP<= RST_VALUE + conv_std_logic_vector(RST_INC,32 );
110  ELSE
111  ADDR_TEMP <= ADDR_TEMP + '1';
112  END IF;
113  END IF;
114  END IF;
115  END IF;
116  END IF;
117  END PROCESS;
118 END ARCHITECTURE;
Ethernet_RAM_TB_AGEN
Definition: Ethernet_RAM_tb_agen.vhd:79