Ethernet_RAM.vhd

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-- You must compile the wrapper file Ethernet_RAM.vhd when simulating
-- the core, Ethernet_RAM. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".

-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY Ethernet_RAM IS
  PORT (
    a : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
    d : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
    clk : IN STD_LOGIC;
    we : IN STD_LOGIC;
    spo : OUT STD_LOGIC_VECTOR(63 DOWNTO 0)
  );
END Ethernet_RAM;

ARCHITECTURE Ethernet_RAM_a OF Ethernet_RAM IS
-- synthesis translate_off
COMPONENT wrapped_Ethernet_RAM
  PORT (
    a : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
    d : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
    clk : IN STD_LOGIC;
    we : IN STD_LOGIC;
    spo : OUT STD_LOGIC_VECTOR(63 DOWNTO 0)
  );
END COMPONENT;

-- Configuration specification
  FOR ALL : wrapped_Ethernet_RAM USE ENTITY XilinxCoreLib.dist_mem_gen_v7_2(behavioral)
    GENERIC MAP (
      c_addr_width  => 11,
      c_default_data  => "0",
      c_depth  => 2048,
      c_family  => "virtex4",
      c_has_clk  => 1,
      c_has_d  => 1,
      c_has_dpo  => 0,
      c_has_dpra  => 0,
      c_has_i_ce  => 0,
      c_has_qdpo  => 0,
      c_has_qdpo_ce  => 0,
      c_has_qdpo_clk  => 0,
      c_has_qdpo_rst  => 0,
      c_has_qdpo_srst  => 0,
      c_has_qspo  => 0,
      c_has_qspo_ce  => 0,
      c_has_qspo_rst  => 0,
      c_has_qspo_srst  => 0,
      c_has_spo  => 1,
      c_has_spra  => 0,
      c_has_we  => 1,
      c_mem_init_file  => "no_coe_file_loaded",
      c_mem_type  => 1,
      c_parser_type  => 1,
      c_pipeline_stages  => 0,
      c_qce_joined  => 0,
      c_qualify_we  => 0,
      c_read_mif  => 0,
      c_reg_a_d_inputs => 0,
      c_reg_dpra_input => 0,
      c_sync_enable  => 1,
      c_width  => 64
    );
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_Ethernet_RAM
  PORT MAP (
    a  => a,
    d  => d,
    clk  => clk,
    we  => we,
    spo  => spo
  );
-- synthesis translate_on

END Ethernet_RAM_a;