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ADDR_FIFO_tb.vhd
1
--------------------------------------------------------------------------------
2
--
3
-- FIFO Generator Core Demo Testbench
4
--
5
--------------------------------------------------------------------------------
6
--
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-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
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--
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-- This file contains confidential and proprietary information
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-- of Xilinx, Inc. and is protected under U.S. and
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-- international copyright and other intellectual property
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-- laws.
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--
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-- DISCLAIMER
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-- This disclaimer is not a license and does not grant any
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-- rights to the materials distributed herewith. Except as
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-- otherwise provided in a valid license issued to you by
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-- Xilinx, and to the maximum extent permitted by applicable
19
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
20
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
21
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
22
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
23
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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-- (2) Xilinx shall not be liable (whether in contract or tort,
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-- including negligence, or under any other theory of
26
-- liability) for any loss or damage of any kind or nature
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-- related to, arising under or in connection with these
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-- materials, including for any direct, or any indirect,
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-- special, incidental, or consequential loss or damage
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-- (including loss of data, profits, goodwill, or any type of
31
-- loss or damage suffered as a result of any action brought
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-- by a third party) even if such damage or loss was
33
-- reasonably foreseeable or Xilinx had been advised of the
34
-- possibility of the same.
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--
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-- CRITICAL APPLICATIONS
37
-- Xilinx products are not designed or intended to be fail-
38
-- safe, or for use in any application requiring fail-safe
39
-- performance, such as life-support or safety devices or
40
-- systems, Class III medical devices, nuclear facilities,
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-- applications related to the deployment of airbags, or any
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-- other applications that could lead to death, personal
43
-- injury, or severe property or environmental damage
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-- (individually and collectively, "Critical
45
-- Applications"). Customer assumes the sole risk and
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-- liability of any use of Xilinx products in Critical
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-- Applications, subject only to applicable laws and
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-- regulations governing limitations on product liability.
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--
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-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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-- PART OF THIS FILE AT ALL TIMES.
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--------------------------------------------------------------------------------
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--
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-- Filename: ADDR_FIFO_tb.vhd
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--
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-- Description:
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-- This is the demo testbench top file for fifo_generator core.
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--
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--------------------------------------------------------------------------------
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-- Library Declarations
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--------------------------------------------------------------------------------
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LIBRARY
ieee
;
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LIBRARY
std
;
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USE
ieee.std_logic_1164.
ALL
;
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USE
ieee.std_logic_unsigned.
ALL
;
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USE
IEEE.std_logic_arith.
ALL
;
67
USE
IEEE.std_logic_misc.
ALL
;
68
USE
ieee.numeric_std.
ALL
;
69
USE
ieee.std_logic_textio.
ALL
;
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USE
std.textio.
ALL
;
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72
LIBRARY
work
;
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USE
work.ADDR_FIFO_pkg.
ALL
;
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75
ENTITY
ADDR_FIFO_tb
IS
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END
ENTITY
;
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78
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ARCHITECTURE
ADDR_FIFO_arch
OF
ADDR_FIFO_tb
IS
80
SIGNAL
status
:
STD_LOGIC_VECTOR
(
7
DOWNTO
0
)
:=
"00000000"
;
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SIGNAL
wr_clk
:
STD_LOGIC
;
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SIGNAL
reset
:
STD_LOGIC
;
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SIGNAL
sim_done
:
STD_LOGIC
:=
'
0
'
;
84
SIGNAL
end_of_sim
:
STD_LOGIC_VECTOR
(
4
DOWNTO
0
)
:=
(
OTHERS
=
>
'
0
'
)
;
85
-- Write and Read clock periods
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CONSTANT
wr_clk_period_by_2
:
TIME
:=
100
ns
;
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-- Procedures to display strings
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PROCEDURE
disp_str(
CONSTANT
str:
IN
STRING
)
IS
89
variable
dp_l
:
line
:=
null
;
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BEGIN
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write
(
dp_l
,
str
)
;
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writeline
(
output
,
dp_l
)
;
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END
PROCEDURE
;
94
95
PROCEDURE
disp_hex(
signal
hex:
IN
STD_LOGIC_VECTOR
(
7
DOWNTO
0
))
IS
96
variable
dp_lx
:
line
:=
null
;
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BEGIN
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hwrite
(
dp_lx
,
hex
)
;
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writeline
(
output
,
dp_lx
)
;
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END
PROCEDURE
;
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102
BEGIN
103
104
-- Generation of clock
105
106
PROCESS
BEGIN
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WAIT
FOR
200
ns
;
-- Wait for global reset
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WHILE
1
=
1
LOOP
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wr_clk
<=
'
0
'
;
110
WAIT
FOR
wr_clk_period_by_2
;
111
wr_clk
<=
'
1
'
;
112
WAIT
FOR
wr_clk_period_by_2
;
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END
LOOP
;
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END
PROCESS
;
115
116
-- Generation of Reset
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118
PROCESS
BEGIN
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reset
<=
'
1
'
;
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WAIT
FOR
2100
ns
;
121
reset
<=
'
0
'
;
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WAIT
;
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END
PROCESS
;
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125
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-- Error message printing based on STATUS signal from ADDR_FIFO_synth
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PROCESS
(status)
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BEGIN
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IF
(
status
/=
"0"
AND
status
/=
"1"
)
THEN
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disp_str
(
"STATUS:"
)
;
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disp_hex
(
status
)
;
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END
IF
;
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135
IF
(
status
(
7
)
=
'
1
'
)
THEN
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assert
false
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report
"Data mismatch found"
138
severity
error
;
139
END
IF
;
140
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IF
(
status
(
1
)
=
'
1
'
)
THEN
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END
IF
;
143
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IF
(
status
(
5
)
=
'
1
'
)
THEN
145
assert
false
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report
"Empty flag Mismatch/timeout"
147
severity
error
;
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END
IF
;
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IF
(
status
(
6
)
=
'
1
'
)
THEN
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assert
false
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report
"Full Flag Mismatch/timeout"
153
severity
error
;
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END
IF
;
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END
PROCESS
;
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157
158
PROCESS
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BEGIN
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wait
until
sim_done
=
'
1
'
;
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IF
(
status
/=
"0"
AND
status
/=
"1"
)
THEN
162
assert
false
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report
"Simulation failed"
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severity
failure
;
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ELSE
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assert
false
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report
"Test Completed Successfully"
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severity
failure
;
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END
IF
;
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END
PROCESS
;
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172
PROCESS
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BEGIN
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wait
for
400
ms
;
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assert
false
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report
"Test bench timed out"
177
severity
failure
;
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END
PROCESS
;
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-- Instance of ADDR_FIFO_synth
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182
ADDR_FIFO_synth_inst:
ADDR_FIFO_synth
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GENERIC
MAP
(
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FREEZEON_ERROR =>
0
,
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TB_STOP_CNT =>
2
,
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TB_SEED =>
67
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)
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PORT
MAP
(
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CLK => wr_clk ,
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RESET => reset,
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SIM_DONE => sim_done,
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STATUS => status
193
)
;
194
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END
ARCHITECTURE
;
ADDR_FIFO_synth
Definition:
ADDR_FIFO_synth.vhd:80
ADDR_FIFO_tb
Definition:
ADDR_FIFO_tb.vhd:75
otsdaq_prepmodernization
firmware
g-2
KickerControllerFirmware
ipcore_dir
ADDR_FIFO
simulation
ADDR_FIFO_tb.vhd
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