ADDR_FIFO_dverif.vhd

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--
-- FIFO Generator Core Demo Testbench 
--
--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
--
-- Filename: ADDR_FIFO_dverif.vhd
--
-- Description:
--   Used for FIFO read interface stimulus generation and data checking
--
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-- Library Declarations
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LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;

LIBRARY work;
USE work.ADDR_FIFO_pkg.ALL;

ENTITY ADDR_FIFO_dverif IS
  GENERIC(
   C_DIN_WIDTH        : INTEGER := 0;
   C_DOUT_WIDTH       : INTEGER := 0;
   C_USE_EMBEDDED_REG : INTEGER := 0;
   C_CH_TYPE          : INTEGER := 0;
   TB_SEED            : INTEGER := 2
  );
  PORT(
       RESET          : IN STD_LOGIC;
       RD_CLK         : IN STD_LOGIC;
       PRC_RD_EN      : IN STD_LOGIC;
       EMPTY          : IN STD_LOGIC;
       DATA_OUT       : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
       RD_EN          : OUT STD_LOGIC;
       DOUT_CHK       : OUT STD_LOGIC
      );
END ENTITY;


ARCHITECTURE fg_dv_arch OF ADDR_FIFO_dverif IS
 
 CONSTANT C_DATA_WIDTH    : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
 CONSTANT EXTRA_WIDTH     : INTEGER := if_then_else(C_CH_TYPE = 2,1,0);
 CONSTANT LOOP_COUNT      : INTEGER := divroundup(C_DATA_WIDTH+EXTRA_WIDTH,8);

 SIGNAL expected_dout     : STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
 SIGNAL data_chk          : STD_LOGIC := '1';
 SIGNAL rand_num          : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 downto 0);
 SIGNAL rd_en_i           : STD_LOGIC := '0';
 SIGNAL pr_r_en           : STD_LOGIC := '0';
 SIGNAL rd_en_d1          : STD_LOGIC := '0';
BEGIN

 
  DOUT_CHK <= data_chk;
  RD_EN    <= rd_en_i;
  rd_en_i  <= PRC_RD_EN;
  
 
  data_fifo_chk:IF(C_CH_TYPE /=2) GENERATE 
  -------------------------------------------------------
  -- Expected data generation and checking for data_fifo
  -------------------------------------------------------
      PROCESS (RD_CLK,RESET)
      BEGIN
        IF (RESET = '1') THEN
          rd_en_d1 <= '0';
        ELSIF (RD_CLK'event AND RD_CLK='1') THEN
          IF(EMPTY = '0' AND rd_en_i='1' AND rd_en_d1 = '0') THEN
            rd_en_d1 <= '1';
          END IF;
        END IF;
      END PROCESS;
   
      pr_r_en       <= rd_en_i AND NOT EMPTY AND rd_en_d1;
      expected_dout <= rand_num(C_DOUT_WIDTH-1 DOWNTO 0);

    gen_num:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
      rd_gen_inst2:ADDR_FIFO_rng
      GENERIC MAP(
                WIDTH  => 8,
                SEED   => TB_SEED+N 
                 )
      PORT MAP(
                CLK         => RD_CLK,
            RESET       => RESET,
                RANDOM_NUM  => rand_num(8*(N+1)-1 downto 8*N),
                ENABLE      => pr_r_en      
              );
    END GENERATE;    
    
      PROCESS (RD_CLK,RESET)
      BEGIN
        IF(RESET = '1') THEN
          data_chk <= '0';
        ELSIF (RD_CLK'event AND RD_CLK='1') THEN
          IF((EMPTY = '0') AND (rd_en_i = '1' AND rd_en_d1 = '1')) THEN
            IF(DATA_OUT = expected_dout) THEN
              data_chk <= '0';
            ELSE
              data_chk <= '1';
            END IF;
          END IF;
        END IF;
      END PROCESS;
  END GENERATE data_fifo_chk;

END ARCHITECTURE;