tdaq-develop-2025-02-12
|
Libraries | |
ieee | |
XilinxCoreLib |
Use Clauses | |
std_logic_1164 |
Ports | ||
clk | in | STD_LOGIC |
srst | in | STD_LOGIC |
din | in | STD_LOGIC_VECTOR ( 47 DOWNTO 0 ) |
wr_en | in | STD_LOGIC |
rd_en | in | STD_LOGIC |
dout | out | STD_LOGIC_VECTOR ( 47 DOWNTO 0 ) |
full | out | STD_LOGIC |
empty | out | STD_LOGIC |
Definition at line 43 of file ADDR_FIFO.vhd.