tdaq-develop-2025-02-12
ADDR_FIFO.vhd
1 --------------------------------------------------------------------------------
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28 --------------------------------------------------------------------------------
29 -- You must compile the wrapper file ADDR_FIFO.vhd when simulating
30 -- the core, ADDR_FIFO. When compiling the wrapper file, be sure to
31 -- reference the XilinxCoreLib VHDL simulation library. For detailed
32 -- instructions, please refer to the "CORE Generator Help".
33 
34 -- The synthesis directives "translate_off/translate_on" specified
35 -- below are supported by Xilinx, Mentor Graphics and Synplicity
36 -- synthesis tools. Ensure they are correct for your synthesis tool(s).
37 
38 LIBRARY ieee;
39 USE ieee.std_logic_1164.ALL;
40 -- synthesis translate_off
41 LIBRARY XilinxCoreLib;
42 -- synthesis translate_on
43 ENTITY ADDR_FIFO IS
44  PORT (
45  clk : IN STD_LOGIC;
46  srst : IN STD_LOGIC;
47  din : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
48  wr_en : IN STD_LOGIC;
49  rd_en : IN STD_LOGIC;
50  dout : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
51  full : OUT STD_LOGIC;
52  empty : OUT STD_LOGIC
53  );
54 END ADDR_FIFO;
55 
56 ARCHITECTURE ADDR_FIFO_a OF ADDR_FIFO IS
57 -- synthesis translate_off
58 COMPONENT wrapped_ADDR_FIFO
59  PORT (
60  clk : IN STD_LOGIC;
61  srst : IN STD_LOGIC;
62  din : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
63  wr_en : IN STD_LOGIC;
64  rd_en : IN STD_LOGIC;
65  dout : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
66  full : OUT STD_LOGIC;
67  empty : OUT STD_LOGIC
68  );
69 END COMPONENT;
70 
71 -- Configuration specification
72  FOR ALL : wrapped_ADDR_FIFO USE ENTITY XilinxCoreLib.fifo_generator_v9_3(behavioral)
73  GENERIC MAP (
74  c_add_ngc_constraint => 0,
75  c_application_type_axis => 0,
76  c_application_type_rach => 0,
77  c_application_type_rdch => 0,
78  c_application_type_wach => 0,
79  c_application_type_wdch => 0,
80  c_application_type_wrch => 0,
81  c_axi_addr_width => 32,
82  c_axi_aruser_width => 1,
83  c_axi_awuser_width => 1,
84  c_axi_buser_width => 1,
85  c_axi_data_width => 64,
86  c_axi_id_width => 4,
87  c_axi_ruser_width => 1,
88  c_axi_type => 0,
89  c_axi_wuser_width => 1,
90  c_axis_tdata_width => 64,
91  c_axis_tdest_width => 4,
92  c_axis_tid_width => 8,
93  c_axis_tkeep_width => 4,
94  c_axis_tstrb_width => 4,
95  c_axis_tuser_width => 4,
96  c_axis_type => 0,
97  c_common_clock => 1,
98  c_count_type => 0,
99  c_data_count_width => 4,
100  c_default_value => "BlankString",
101  c_din_width => 48,
102  c_din_width_axis => 1,
103  c_din_width_rach => 32,
104  c_din_width_rdch => 64,
105  c_din_width_wach => 32,
106  c_din_width_wdch => 64,
107  c_din_width_wrch => 2,
108  c_dout_rst_val => "0",
109  c_dout_width => 48,
110  c_enable_rlocs => 0,
111  c_enable_rst_sync => 1,
112  c_error_injection_type => 0,
113  c_error_injection_type_axis => 0,
114  c_error_injection_type_rach => 0,
115  c_error_injection_type_rdch => 0,
116  c_error_injection_type_wach => 0,
117  c_error_injection_type_wdch => 0,
118  c_error_injection_type_wrch => 0,
119  c_family => "virtex4",
120  c_full_flags_rst_val => 0,
121  c_has_almost_empty => 0,
122  c_has_almost_full => 0,
123  c_has_axi_aruser => 0,
124  c_has_axi_awuser => 0,
125  c_has_axi_buser => 0,
126  c_has_axi_rd_channel => 0,
127  c_has_axi_ruser => 0,
128  c_has_axi_wr_channel => 0,
129  c_has_axi_wuser => 0,
130  c_has_axis_tdata => 0,
131  c_has_axis_tdest => 0,
132  c_has_axis_tid => 0,
133  c_has_axis_tkeep => 0,
134  c_has_axis_tlast => 0,
135  c_has_axis_tready => 1,
136  c_has_axis_tstrb => 0,
137  c_has_axis_tuser => 0,
138  c_has_backup => 0,
139  c_has_data_count => 0,
140  c_has_data_counts_axis => 0,
141  c_has_data_counts_rach => 0,
142  c_has_data_counts_rdch => 0,
143  c_has_data_counts_wach => 0,
144  c_has_data_counts_wdch => 0,
145  c_has_data_counts_wrch => 0,
146  c_has_int_clk => 0,
147  c_has_master_ce => 0,
148  c_has_meminit_file => 0,
149  c_has_overflow => 0,
150  c_has_prog_flags_axis => 0,
151  c_has_prog_flags_rach => 0,
152  c_has_prog_flags_rdch => 0,
153  c_has_prog_flags_wach => 0,
154  c_has_prog_flags_wdch => 0,
155  c_has_prog_flags_wrch => 0,
156  c_has_rd_data_count => 0,
157  c_has_rd_rst => 0,
158  c_has_rst => 0,
159  c_has_slave_ce => 0,
160  c_has_srst => 1,
161  c_has_underflow => 0,
162  c_has_valid => 0,
163  c_has_wr_ack => 0,
164  c_has_wr_data_count => 0,
165  c_has_wr_rst => 0,
166  c_implementation_type => 0,
167  c_implementation_type_axis => 1,
168  c_implementation_type_rach => 1,
169  c_implementation_type_rdch => 1,
170  c_implementation_type_wach => 1,
171  c_implementation_type_wdch => 1,
172  c_implementation_type_wrch => 1,
173  c_init_wr_pntr_val => 0,
174  c_interface_type => 0,
175  c_memory_type => 2,
176  c_mif_file_name => "BlankString",
177  c_msgon_val => 1,
178  c_optimization_mode => 0,
179  c_overflow_low => 0,
180  c_preload_latency => 1,
181  c_preload_regs => 0,
182  c_prim_fifo_type => "512x72",
183  c_prog_empty_thresh_assert_val => 2,
184  c_prog_empty_thresh_assert_val_axis => 1022,
185  c_prog_empty_thresh_assert_val_rach => 1022,
186  c_prog_empty_thresh_assert_val_rdch => 1022,
187  c_prog_empty_thresh_assert_val_wach => 1022,
188  c_prog_empty_thresh_assert_val_wdch => 1022,
189  c_prog_empty_thresh_assert_val_wrch => 1022,
190  c_prog_empty_thresh_negate_val => 3,
191  c_prog_empty_type => 0,
192  c_prog_empty_type_axis => 0,
193  c_prog_empty_type_rach => 0,
194  c_prog_empty_type_rdch => 0,
195  c_prog_empty_type_wach => 0,
196  c_prog_empty_type_wdch => 0,
197  c_prog_empty_type_wrch => 0,
198  c_prog_full_thresh_assert_val => 14,
199  c_prog_full_thresh_assert_val_axis => 1023,
200  c_prog_full_thresh_assert_val_rach => 1023,
201  c_prog_full_thresh_assert_val_rdch => 1023,
202  c_prog_full_thresh_assert_val_wach => 1023,
203  c_prog_full_thresh_assert_val_wdch => 1023,
204  c_prog_full_thresh_assert_val_wrch => 1023,
205  c_prog_full_thresh_negate_val => 13,
206  c_prog_full_type => 0,
207  c_prog_full_type_axis => 0,
208  c_prog_full_type_rach => 0,
209  c_prog_full_type_rdch => 0,
210  c_prog_full_type_wach => 0,
211  c_prog_full_type_wdch => 0,
212  c_prog_full_type_wrch => 0,
213  c_rach_type => 0,
214  c_rd_data_count_width => 4,
215  c_rd_depth => 16,
216  c_rd_freq => 1,
217  c_rd_pntr_width => 4,
218  c_rdch_type => 0,
219  c_reg_slice_mode_axis => 0,
220  c_reg_slice_mode_rach => 0,
221  c_reg_slice_mode_rdch => 0,
222  c_reg_slice_mode_wach => 0,
223  c_reg_slice_mode_wdch => 0,
224  c_reg_slice_mode_wrch => 0,
225  c_synchronizer_stage => 2,
226  c_underflow_low => 0,
227  c_use_common_overflow => 0,
228  c_use_common_underflow => 0,
229  c_use_default_settings => 0,
230  c_use_dout_rst => 1,
231  c_use_ecc => 0,
232  c_use_ecc_axis => 0,
233  c_use_ecc_rach => 0,
234  c_use_ecc_rdch => 0,
235  c_use_ecc_wach => 0,
236  c_use_ecc_wdch => 0,
237  c_use_ecc_wrch => 0,
238  c_use_embedded_reg => 0,
239  c_use_fifo16_flags => 0,
240  c_use_fwft_data_count => 0,
241  c_valid_low => 0,
242  c_wach_type => 0,
243  c_wdch_type => 0,
244  c_wr_ack_low => 0,
245  c_wr_data_count_width => 4,
246  c_wr_depth => 16,
247  c_wr_depth_axis => 1024,
248  c_wr_depth_rach => 16,
249  c_wr_depth_rdch => 1024,
250  c_wr_depth_wach => 16,
251  c_wr_depth_wdch => 1024,
252  c_wr_depth_wrch => 16,
253  c_wr_freq => 1,
254  c_wr_pntr_width => 4,
255  c_wr_pntr_width_axis => 10,
256  c_wr_pntr_width_rach => 4,
257  c_wr_pntr_width_rdch => 10,
258  c_wr_pntr_width_wach => 4,
259  c_wr_pntr_width_wdch => 10,
260  c_wr_pntr_width_wrch => 4,
261  c_wr_response_latency => 1,
262  c_wrch_type => 0
263  );
264 -- synthesis translate_on
265 BEGIN
266 -- synthesis translate_off
267 U0 : wrapped_ADDR_FIFO
268  PORT MAP (
269  clk => clk,
270  srst => srst,
271  din => din,
272  wr_en => wr_en,
273  rd_en => rd_en,
274  dout => dout,
275  full => full,
276  empty => empty
277  );
278 -- synthesis translate_on
279 
280 END ADDR_FIFO_a;
ADDR_FIFO
Definition: ADDR_FIFO.vhd:43