fifo_adc_dgen.vhd

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--
-- FIFO Generator Core Demo Testbench 
--
--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
--
-- Filename: fifo_adc_dgen.vhd
--
-- Description:
--   Used for write interface stimulus generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;

LIBRARY work;
USE work.fifo_adc_pkg.ALL;

ENTITY fifo_adc_dgen IS
  GENERIC (
        C_DIN_WIDTH   : INTEGER := 32;
        C_DOUT_WIDTH  : INTEGER := 32;
        C_CH_TYPE     : INTEGER := 0;
        TB_SEED       : INTEGER := 2
     );
  PORT (
        RESET     : IN STD_LOGIC;
        WR_CLK    : IN STD_LOGIC;
        PRC_WR_EN : IN STD_LOGIC;
        FULL      : IN STD_LOGIC;  
        WR_EN     : OUT STD_LOGIC;      
        WR_DATA   : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
       );
END ENTITY;


ARCHITECTURE fg_dg_arch OF fifo_adc_dgen IS
 
  CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
  CONSTANT LOOP_COUNT   : INTEGER := divroundup(C_DATA_WIDTH,8);
  CONSTANT D_WIDTH_DIFF : INTEGER := log2roundup(C_DOUT_WIDTH/C_DIN_WIDTH);
  
  SIGNAL pr_w_en        : STD_LOGIC := '0';
  SIGNAL rand_num       : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0);
  SIGNAL wr_data_i      : STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
  SIGNAL wr_d_sel       : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '0');
 BEGIN
  
   WR_EN   <= PRC_WR_EN ;
   WR_DATA <= wr_data_i AFTER 100 ns;

  ----------------------------------------------
  -- Generation of DATA
  ----------------------------------------------
  gen_stim:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
    rd_gen_inst1:fifo_adc_rng
    GENERIC MAP(
               WIDTH  => 8,
               SEED   => TB_SEED+N 
               )
    PORT MAP(
              CLK         => WR_CLK,
          RESET       => RESET,
              RANDOM_NUM  => rand_num(8*(N+1)-1 downto 8*N),
              ENABLE      => pr_w_en
            );
  END GENERATE; 

     pr_w_en <= (AND_REDUCE(wr_d_sel)) AND PRC_WR_EN AND NOT FULL;
     wr_data_i <=  rand_num(C_DOUT_WIDTH-C_DIN_WIDTH*conv_integer(wr_d_sel)-1 DOWNTO C_DOUT_WIDTH-C_DIN_WIDTH*(conv_integer(wr_d_sel)+1));
          
     PROCESS(WR_CLK,RESET)
     BEGIN
       IF(RESET = '1') THEN
           wr_d_sel  <= (OTHERS => '0');
       ELSIF(WR_CLK'event AND WR_CLK = '1') THEN
         IF(FULL = '0' AND PRC_WR_EN = '1') THEN
           wr_d_sel  <= wr_d_sel + "1";
         END IF;
       END IF;
     END PROCESS;     


END ARCHITECTURE;