otsdaq_prepmodernization  v2_05_02_indev
ethernetFIFO_rng.vhd
1 --------------------------------------------------------------------------------
2 --
3 -- FIFO Generator Core Demo Testbench
4 --
5 --------------------------------------------------------------------------------
6 --
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52 --------------------------------------------------------------------------------
53 --
54 -- Filename: ethernetFIFO_rng.vhd
55 --
56 -- Description:
57 -- Used for generation of pseudo random numbers
58 --
59 --------------------------------------------------------------------------------
60 -- Library Declarations
61 --------------------------------------------------------------------------------
62 LIBRARY ieee;
63 USE ieee.std_logic_1164.ALL;
64 USE ieee.std_logic_unsigned.all;
65 USE IEEE.std_logic_arith.all;
66 USE IEEE.std_logic_misc.all;
67 
69  GENERIC (
70  WIDTH : integer := 8;
71  SEED : integer := 3);
72  PORT (
73  CLK : IN STD_LOGIC;
74  RESET : IN STD_LOGIC;
75  ENABLE : IN STD_LOGIC;
76  RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0));
77 END ENTITY;
78 
79 ARCHITECTURE rg_arch OF ethernetFIFO_rng IS
80 BEGIN
81 PROCESS (CLK,RESET)
82  VARIABLE rand_temp : STD_LOGIC_VECTOR(width-1 DOWNTO 0):=conv_std_logic_vector(SEED,width);
83  VARIABLE temp : STD_LOGIC := '0';
84 BEGIN
85  IF(RESET = '1') THEN
86  rand_temp := conv_std_logic_vector(SEED,width);
87  temp := '0';
88  ELSIF (CLK'event AND CLK = '1') THEN
89  IF (ENABLE = '1') THEN
90  temp := rand_temp(width-1) xnor rand_temp(width-3) xnor rand_temp(width-4) xnor rand_temp(width-5);
91  rand_temp(width-1 DOWNTO 1) := rand_temp(width-2 DOWNTO 0);
92  rand_temp(0) := temp;
93  END IF;
94  END IF;
95 
96  RANDOM_NUM <= rand_temp;
97 
98 END PROCESS;
99 
100 END ARCHITECTURE;