otsdaq_prepmodernization  v2_05_02_indev
gec_rx_ctl_0 Entity Reference

Libraries

IEEE 

Use Clauses

IEEE.std_logic_1164.all 
IEEE.std_logic_arith.all 
IEEE.std_logic_unsigned.all 
params_package.all 

Ports

block_en   in STD_LOGIC
clock   in STD_LOGIC
data_fifo_full   in STD_LOGIC
data_fifo_wrerr   in STD_LOGIC
gec_user_crc_err   in STD_LOGIC
gec_user_rx_size_out   in STD_LOGIC_VECTOR ( 10 downto 0 )
gec_user_rx_valid_out   in STD_LOGIC
reset_n   in STD_LOGIC
crc_err_flag   out STD_LOGIC
data_fifo_wren   out STD_LOGIC
gec_rx_ctl_mux_sel   out STD_LOGIC
gec_rx_ctl_stat_out   out STD_LOGIC_VECTOR ( 7 downto 0 )
info_fifo_wr_data   out STD_LOGIC_VECTOR ( 15 downto 0 )
info_fifo_wren   out STD_LOGIC
rx_size_err_flag   out STD_LOGIC

Detailed Description

Definition at line 27 of file GEC_RX_CTL_0.vhd.


The documentation for this class was generated from the following file: