fifo_adc_dverif Entity Reference

Libraries
ieee
work

Use Clauses
ieee.std_logic_1164.all
ieee.std_logic_unsigned.all
IEEE.std_logic_arith.all
IEEE.std_logic_misc.all
work.fifo_adc_pkg.all

Generics
C_DIN_WIDTH	INTEGER := 0
C_DOUT_WIDTH	INTEGER := 0
C_USE_EMBEDDED_REG	INTEGER := 0
C_CH_TYPE	INTEGER := 0
TB_SEED	INTEGER := 2

Ports
RESET	in STD_LOGIC
RD_CLK	in STD_LOGIC
PRC_RD_EN	in STD_LOGIC
EMPTY	in STD_LOGIC
DATA_OUT	in STD_LOGIC_VECTOR ( C_DOUT_WIDTH - 1 downto 0 )
RD_EN	out STD_LOGIC
DOUT_CHK	out STD_LOGIC

Detailed Description

Definition at line 71 of file fifo_adc_dverif.vhd.

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The documentation for this class was generated from the following file:

• otsdaq_prepmodernization/firmware/g-2/KickerControllerFirmware/GEL_CAPTAN/ipcore_dir/fifo_adc/simulation/fifo_adc_dverif.vhd