bmg_wrapper Entity Reference

Libraries
IEEE
UNISIM

Use Clauses
IEEE.STD_LOGIC_1164.all
IEEE.STD_LOGIC_ARITH.all
IEEE.STD_LOGIC_UNSIGNED.all
UNISIM.VCOMPONENTS.all

Ports
CLKA	in STD_LOGIC
RSTA	in STD_LOGIC
ENA	in STD_LOGIC
REGCEA	in STD_LOGIC
WEA	in STD_LOGIC_VECTOR ( 0 downto 0 )
ADDRA	in STD_LOGIC_VECTOR ( 9 downto 0 )
DINA	in STD_LOGIC_VECTOR ( 7 downto 0 )
DOUTA	out STD_LOGIC_VECTOR ( 7 downto 0 )
CLKB	in STD_LOGIC
RSTB	in STD_LOGIC
ENB	in STD_LOGIC
REGCEB	in STD_LOGIC
WEB	in STD_LOGIC_VECTOR ( 0 downto 0 )
ADDRB	in STD_LOGIC_VECTOR ( 9 downto 0 )
DINB	in STD_LOGIC_VECTOR ( 7 downto 0 )
DOUTB	out STD_LOGIC_VECTOR ( 7 downto 0 )
INJECTSBITERR	in STD_LOGIC
INJECTDBITERR	in STD_LOGIC
SBITERR	out STD_LOGIC
DBITERR	out STD_LOGIC
RDADDRECC	out STD_LOGIC_VECTOR ( 9 downto 0 )
S_ACLK	in STD_LOGIC
S_AXI_AWID	in STD_LOGIC_VECTOR ( 3 downto 0 )
S_AXI_AWADDR	in STD_LOGIC_VECTOR ( 31 downto 0 )
S_AXI_AWLEN	in STD_LOGIC_VECTOR ( 7 downto 0 )
S_AXI_AWSIZE	in STD_LOGIC_VECTOR ( 2 downto 0 )
S_AXI_AWBURST	in STD_LOGIC_VECTOR ( 1 downto 0 )
S_AXI_AWVALID	in STD_LOGIC
S_AXI_AWREADY	out STD_LOGIC
S_AXI_WDATA	in STD_LOGIC_VECTOR ( 7 downto 0 )
S_AXI_WSTRB	in STD_LOGIC_VECTOR ( 0 downto 0 )
S_AXI_WLAST	in STD_LOGIC
S_AXI_WVALID	in STD_LOGIC
S_AXI_WREADY	out STD_LOGIC
S_AXI_BID	out STD_LOGIC_VECTOR ( 3 downto 0 ) := ( others = > ' 0 ' )
S_AXI_BRESP	out STD_LOGIC_VECTOR ( 1 downto 0 )
S_AXI_BVALID	out STD_LOGIC
S_AXI_BREADY	in STD_LOGIC
S_AXI_ARID	in STD_LOGIC_VECTOR ( 3 downto 0 )
S_AXI_ARADDR	in STD_LOGIC_VECTOR ( 31 downto 0 )
S_AXI_ARLEN	in STD_LOGIC_VECTOR ( 7 downto 0 )
S_AXI_ARSIZE	in STD_LOGIC_VECTOR ( 2 downto 0 )
S_AXI_ARBURST	in STD_LOGIC_VECTOR ( 1 downto 0 )
S_AXI_ARVALID	in STD_LOGIC
S_AXI_ARREADY	out STD_LOGIC
S_AXI_RID	out STD_LOGIC_VECTOR ( 3 downto 0 ) := ( others = > ' 0 ' )
S_AXI_RDATA	out STD_LOGIC_VECTOR ( 7 downto 0 )
S_AXI_RRESP	out STD_LOGIC_VECTOR ( 1 downto 0 )
S_AXI_RLAST	out STD_LOGIC
S_AXI_RVALID	out STD_LOGIC
S_AXI_RREADY	in STD_LOGIC
S_AXI_INJECTSBITERR	in STD_LOGIC
S_AXI_INJECTDBITERR	in STD_LOGIC
S_AXI_SBITERR	out STD_LOGIC
S_AXI_DBITERR	out STD_LOGIC
S_AXI_RDADDRECC	out STD_LOGIC_VECTOR ( 9 downto 0 )
S_ARESETN	in STD_LOGIC

Detailed Description

Definition at line 143 of file bmg_wrapper.vhd.

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The documentation for this class was generated from the following file:

• otsdaq_prepmodernization/firmware/g-2/KickerControllerFirmware/coregen/fadc_mem_ste/example_design/bmg_wrapper.vhd