INFO_FIFO64_0 Entity Reference

Libraries
ieee
XilinxCoreLib

Use Clauses
ieee.std_logic_1164.all

Ports
clk	in std_logic
din	in std_logic_VECTOR ( 63 downto 0 )
rd_en	in std_logic
srst	in std_logic
wr_en	in std_logic
dout	out std_logic_VECTOR ( 63 downto 0 )
empty	out std_logic
full	out std_logic

Detailed Description

Definition at line 43 of file INFO_FIFO64_0.vhd.

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The documentation for this class was generated from the following file:

• otsdaq_prepmodernization/firmware/g-2/KickerControllerFirmware/GEL_CAPTAN/INFO_FIFO64_0.vhd