ClockLatchSignals Entity Reference

Libraries
IEEE

Use Clauses
IEEE.NUMERIC_STD.all
IEEE.STD_LOGIC_1164.all
IEEE.STD_LOGIC_UNSIGNED.all

Ports
clk	in STD_LOGIC
rst	in STD_LOGIC
signals	out STD_LOGIC_VECTOR ( 7 downto 0 )

Detailed Description

Definition at line 34 of file ClockLatchSignals.vhd.

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The documentation for this class was generated from the following file:

• otsdaq_prepmodernization/firmware/g-2/KickerControllerFirmware/GEL_CAPTAN/ClockLatchSignals.vhd