otsdaq_prepmodernization
v2_05_02_indev
|
Libraries | |
ieee | |
work |
Use Clauses | |
ieee.std_logic_1164.all | |
ieee.std_logic_unsigned.all | |
IEEE.std_logic_arith.all | |
IEEE.std_logic_misc.all | |
work.ADDR_FIFO_pkg.all |
Generics | |
AXI_CHANNEL | STRING := " NONE " |
C_APPLICATION_TYPE | INTEGER := 0 |
C_DIN_WIDTH | INTEGER := 0 |
C_DOUT_WIDTH | INTEGER := 0 |
C_WR_PNTR_WIDTH | INTEGER := 0 |
C_RD_PNTR_WIDTH | INTEGER := 0 |
C_CH_TYPE | INTEGER := 0 |
FREEZEON_ERROR | INTEGER := 0 |
TB_STOP_CNT | INTEGER := 2 |
TB_SEED | INTEGER := 2 |
Ports | |
RESET_WR | in STD_LOGIC |
RESET_RD | in STD_LOGIC |
WR_CLK | in STD_LOGIC |
RD_CLK | in STD_LOGIC |
FULL | in STD_LOGIC |
EMPTY | in STD_LOGIC |
ALMOST_FULL | in STD_LOGIC |
ALMOST_EMPTY | in STD_LOGIC |
DATA_IN | in STD_LOGIC_VECTOR ( C_DIN_WIDTH - 1 downto 0 ) |
DATA_OUT | in STD_LOGIC_VECTOR ( C_DOUT_WIDTH - 1 downto 0 ) |
DOUT_CHK | in STD_LOGIC |
PRC_WR_EN | out STD_LOGIC |
PRC_RD_EN | out STD_LOGIC |
RESET_EN | out STD_LOGIC |
SIM_DONE | out STD_LOGIC |
STATUS | out STD_LOGIC_VECTOR ( 7 downto 0 ) |
Definition at line 72 of file ADDR_FIFO_pctrl.vhd.