otsdaq_prepmodernization  v2_05_02_indev
burst_test_fifo64.vhd
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28 --------------------------------------------------------------------------------
29 -- You must compile the wrapper file burst_test_fifo64.vhd when simulating
30 -- the core, burst_test_fifo64. When compiling the wrapper file, be sure to
31 -- reference the XilinxCoreLib VHDL simulation library. For detailed
32 -- instructions, please refer to the "CORE Generator Help".
33 
34 -- The synthesis directives "translate_off/translate_on" specified
35 -- below are supported by Xilinx, Mentor Graphics and Synplicity
36 -- synthesis tools. Ensure they are correct for your synthesis tool(s).
37 
38 LIBRARY ieee;
39 USE ieee.std_logic_1164.ALL;
40 -- synthesis translate_off
41 Library XilinxCoreLib;
42 -- synthesis translate_on
43 ENTITY burst_test_fifo64 IS
44  port (
45  din: IN std_logic_VECTOR(63 downto 0);
46  rd_clk: IN std_logic;
47  rd_en: IN std_logic;
48  rst: IN std_logic;
49  wr_clk: IN std_logic;
50  wr_en: IN std_logic;
51  dout: OUT std_logic_VECTOR(63 downto 0);
52  empty: OUT std_logic;
53  full: OUT std_logic);
54 END burst_test_fifo64;
55 
56 ARCHITECTURE burst_test_fifo64_a OF burst_test_fifo64 IS
57 -- synthesis translate_off
58 component wrapped_burst_test_fifo64
59  port (
60  din: IN std_logic_VECTOR(63 downto 0);
61  rd_clk: IN std_logic;
62  rd_en: IN std_logic;
63  rst: IN std_logic;
64  wr_clk: IN std_logic;
65  wr_en: IN std_logic;
66  dout: OUT std_logic_VECTOR(63 downto 0);
67  empty: OUT std_logic;
68  full: OUT std_logic);
69 end component;
70 
71 -- Configuration specification
72  for all : wrapped_burst_test_fifo64 use entity XilinxCoreLib.fifo_generator_v4_3(behavioral)
73  generic map(
74  c_has_int_clk => 0,
75  c_rd_freq => 1,
76  c_wr_response_latency => 1,
77  c_has_srst => 0,
78  c_has_rd_data_count => 0,
79  c_din_width => 64,
80  c_has_wr_data_count => 0,
81  c_full_flags_rst_val => 1,
82  c_implementation_type => 2,
83  c_family => "virtex4",
84  c_use_embedded_reg => 0,
85  c_has_wr_rst => 0,
86  c_wr_freq => 1,
87  c_use_dout_rst => 1,
88  c_underflow_low => 0,
89  c_has_meminit_file => 0,
90  c_has_overflow => 0,
91  c_preload_latency => 1,
92  c_dout_width => 64,
93  c_msgon_val => 1,
94  c_rd_depth => 16,
95  c_default_value => "BlankString",
96  c_mif_file_name => "BlankString",
97  c_has_underflow => 0,
98  c_has_rd_rst => 0,
99  c_has_almost_full => 0,
100  c_has_rst => 1,
101  c_data_count_width => 4,
102  c_has_wr_ack => 0,
103  c_use_ecc => 0,
104  c_wr_ack_low => 0,
105  c_common_clock => 0,
106  c_rd_pntr_width => 4,
107  c_use_fwft_data_count => 0,
108  c_has_almost_empty => 0,
109  c_rd_data_count_width => 4,
110  c_enable_rlocs => 0,
111  c_wr_pntr_width => 4,
112  c_overflow_low => 0,
113  c_prog_empty_type => 0,
114  c_optimization_mode => 0,
115  c_wr_data_count_width => 4,
116  c_preload_regs => 0,
117  c_dout_rst_val => "0",
118  c_has_data_count => 0,
119  c_prog_full_thresh_negate_val => 12,
120  c_wr_depth => 16,
121  c_prog_empty_thresh_negate_val => 3,
122  c_prog_empty_thresh_assert_val => 2,
123  c_has_valid => 0,
124  c_init_wr_pntr_val => 0,
125  c_prog_full_thresh_assert_val => 13,
126  c_use_fifo16_flags => 0,
127  c_has_backup => 0,
128  c_valid_low => 0,
129  c_prim_fifo_type => "512x72",
130  c_count_type => 0,
131  c_prog_full_type => 0,
132  c_memory_type => 1);
133 -- synthesis translate_on
134 BEGIN
135 -- synthesis translate_off
136 U0 : wrapped_burst_test_fifo64
137  port map (
138  din => din,
139  rd_clk => rd_clk,
140  rd_en => rd_en,
141  rst => rst,
142  wr_clk => wr_clk,
143  wr_en => wr_en,
144  dout => dout,
145  empty => empty,
146  full => full);
147 -- synthesis translate_on
148 
149 END burst_test_fifo64_a;
150 
burst_test_fifo64
Definition: burst_test_fifo64.vhd:43