1 --------------------------------------------------------------------------------
3 -- FIFO Generator Core Demo Testbench
5 --------------------------------------------------------------------------------
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52 --------------------------------------------------------------------------------
54 -- Filename: INFO_FIFO_0_synth.vhd
57 -- This is the demo testbench for fifo_generator core.
59 --------------------------------------------------------------------------------
60 -- Library Declarations
61 --------------------------------------------------------------------------------
65 USE ieee.STD_LOGIC_1164.
ALL;
66 USE ieee.STD_LOGIC_unsigned.
ALL;
67 USE IEEE.STD_LOGIC_arith.
ALL;
68 USE ieee.numeric_std.
ALL;
69 USE ieee.STD_LOGIC_misc.
ALL;
75 USE work.INFO_FIFO_0_pkg.
ALL;
77 --------------------------------------------------------------------------------
79 --------------------------------------------------------------------------------
82 FREEZEON_ERROR : := 0;
90 STATUS : OUT (7 DOWNTO 0)
96 -- FIFO interface signal declarations
101 SIGNAL din : (16-1 DOWNTO 0);
102 SIGNAL dout : (16-1 DOWNTO 0);
106 SIGNAL wr_data : (16-1 DOWNTO 0);
107 SIGNAL dout_i : (16-1 DOWNTO 0);
108 SIGNAL wr_en_i : := '0';
109 SIGNAL rd_en_i : := '0';
110 SIGNAL full_i : := '0';
111 SIGNAL empty_i : := '0';
112 SIGNAL almost_full_i : := '0';
113 SIGNAL almost_empty_i : := '0';
114 SIGNAL prc_we_i : := '0';
115 SIGNAL prc_re_i : := '0';
116 SIGNAL dout_chk_i : := '0';
117 SIGNAL rst_int_rd : := '0';
118 SIGNAL rst_int_wr : := '0';
119 SIGNAL rst_gen_rd : (7 DOWNTO 0) := (OTHERS => '0');
120 SIGNAL rst_s_wr3 : := '0';
121 SIGNAL rst_s_rd : := '0';
122 SIGNAL reset_en : := '0';
123 SIGNAL rst_async_rd1 : := '0';
124 SIGNAL rst_async_rd2 : := '0';
125 SIGNAL rst_async_rd3 : := '0';
127 SIGNAL rst_sync_rd1 : := '0';
128 SIGNAL rst_sync_rd2 : := '0';
129 SIGNAL rst_sync_rd3 : := '0';
133 ---- Reset generation logic -----
134 rst_int_wr <= rst_async_rd3 OR rst_s_rd;
135 rst_int_rd <= rst_async_rd3 OR rst_s_rd;
137 --Testbench reset synchronization
141 rst_async_rd1 <= '1';
142 rst_async_rd2 <= '1';
143 rst_async_rd3 <= '1';
144 ELSIF(clk_i'event AND clk_i='1') THEN
145 rst_async_rd1 <= RESET;
146 rst_async_rd2 <= rst_async_rd1;
147 rst_async_rd3 <= rst_async_rd2;
151 --Synchronous reset generation for FIFO core
154 IF(clk_i'event AND clk_i='1') THEN
155 rst_sync_rd1 <= RESET;
156 rst_sync_rd2 <= rst_sync_rd1;
157 rst_sync_rd3 <= rst_sync_rd2;
161 --Soft reset for core and testbench
164 IF(clk_i'event AND clk_i='1') THEN
165 rst_gen_rd <= rst_gen_rd + "1";
166 IF(reset_en = '1' AND AND_REDUCE(rst_gen_rd) = '1') THEN
169 report "Reset applied..Memory Collision checks are not valid"
172 IF(AND_REDUCE(rst_gen_rd) = '1' AND rst_s_rd = '1') THEN
175 report "Reset removed..Memory Collision checks are valid"
183 ---- Clock buffers for testbench ----
187 srst <= rst_sync_rd3 OR rst_s_rd AFTER 50 ns;
202 PORT MAP (
-- Write Port
205 PRC_WR_EN => prc_we_i,
215 C_USE_EMBEDDED_REG =>
0,
222 PRC_RD_EN => prc_re_i,
226 DOUT_CHK => dout_chk_i
231 AXI_CHANNEL =>
"Native",
232 C_APPLICATION_TYPE =>
0,
235 C_WR_PNTR_WIDTH =>
4,
236 C_RD_PNTR_WIDTH =>
4,
238 FREEZEON_ERROR => FREEZEON_ERROR ,
240 TB_STOP_CNT => TB_STOP_CNT
243 RESET_WR => rst_int_wr,
244 RESET_RD => rst_int_rd,
245 RESET_EN => reset_en,
248 PRC_WR_EN => prc_we_i,
249 PRC_RD_EN => prc_re_i,
251 ALMOST_FULL => almost_full_i ,
252 ALMOST_EMPTY => almost_empty_i ,
253 DOUT_CHK => dout_chk_i,
257 SIM_DONE => SIM_DONE,