otsdaq_prepmodernization  v2_05_02_indev
EthernetRAM_tb.vhd
1 --------------------------------------------------------------------------------
2 --
3 -- BLK MEM GEN v7_3 Core - Top File for the Example Testbench
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52 
53 --------------------------------------------------------------------------------
54 -- Filename: EthernetRAM_tb.vhd
55 -- Description:
56 -- Testbench Top
57 --------------------------------------------------------------------------------
58 -- Author: IP Solutions Division
59 --
60 -- History: Sep 12, 2011 - First Release
61 --------------------------------------------------------------------------------
62 --
63 --------------------------------------------------------------------------------
64 -- Library Declarations
65 --------------------------------------------------------------------------------
66 
67 LIBRARY IEEE;
68 USE IEEE.STD_LOGIC_1164.ALL;
69 USE IEEE.STD_LOGIC_ARITH.ALL;
70 USE IEEE.STD_LOGIC_UNSIGNED.ALL;
71 
72 LIBRARY work;
73 USE work.ALL;
74 
75 ENTITY EthernetRAM_tb IS
76 END ENTITY;
77 
78 
79 ARCHITECTURE EthernetRAM_tb_ARCH OF EthernetRAM_tb IS
80  SIGNAL STATUS : STD_LOGIC_VECTOR(8 DOWNTO 0);
81  SIGNAL CLK : STD_LOGIC := '1';
82  SIGNAL RESET : STD_LOGIC;
83 
84  BEGIN
85 
86 
87  CLK_GEN: PROCESS BEGIN
88  CLK <= NOT CLK;
89  WAIT FOR 100 NS;
90  CLK <= NOT CLK;
91  WAIT FOR 100 NS;
92  END PROCESS;
93 
94  RST_GEN: PROCESS BEGIN
95  RESET <= '1';
96  WAIT FOR 1000 NS;
97  RESET <= '0';
98  WAIT;
99  END PROCESS;
100 
101 
102 --STOP_SIM: PROCESS BEGIN
103 -- WAIT FOR 200 US; -- STOP SIMULATION AFTER 1 MS
104 -- ASSERT FALSE
105 -- REPORT "END SIMULATION TIME REACHED"
106 -- SEVERITY FAILURE;
107 --END PROCESS;
108 --
109 PROCESS BEGIN
110  WAIT UNTIL STATUS(8)='1';
111  IF( STATUS(7 downto 0)/="0") THEN
112  ASSERT false
113  REPORT "Test Completed Successfully"
114  SEVERITY NOTE;
115  REPORT "Simulation Failed"
116  SEVERITY FAILURE;
117  ELSE
118  ASSERT false
119  REPORT "TEST PASS"
120  SEVERITY NOTE;
121  REPORT "Test Completed Successfully"
122  SEVERITY FAILURE;
123  END IF;
124 
125 END PROCESS;
126 
127  EthernetRAM_synth_inst:ENTITY work.EthernetRAM_synth
128  PORT MAP(
129  CLK_IN => CLK,
130  RESET_IN => RESET,
131  STATUS => STATUS
132  );
133 
134 END ARCHITECTURE;
EthernetRAM_synth
Definition: EthernetRAM_synth.vhd:94
EthernetRAM_tb
Definition: EthernetRAM_tb.vhd:75