Ethernet_RAM_tb_rng.vhd

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--
-- DIST MEM GEN Core - Random Number Generator
--
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--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
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--
-- Filename: Ethernet_RAM_tb_rng.vhd
--
-- Description:
--   Random Generator
--
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-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
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--
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-- Library Declarations
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LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;


ENTITY Ethernet_RAM_TB_RNG IS
  GENERIC ( 
    WIDTH : INTEGER :=  32;
     SEED  : INTEGER :=2 
  );
        
  PORT (
    CLK        : IN STD_LOGIC;
    RST        : IN STD_LOGIC;
    EN         : IN STD_LOGIC;
    RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0)   --OUTPUT VECTOR           
  );
END Ethernet_RAM_TB_RNG;

ARCHITECTURE BEHAVIORAL OF Ethernet_RAM_TB_RNG IS
BEGIN
  PROCESS(CLK)
    VARIABLE RAND_TEMP : STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0):=CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
    VARIABLE TEMP      : STD_LOGIC := '0';
  BEGIN
    IF(RISING_EDGE(CLK)) THEN
      IF(RST='1') THEN
        RAND_TEMP  := CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
       ELSE
        IF(EN = '1') THEN
          TEMP                        := RAND_TEMP(WIDTH-1) XOR RAND_TEMP(WIDTH-2);
          RAND_TEMP(WIDTH-1 DOWNTO 1) := RAND_TEMP(WIDTH-2 DOWNTO 0);
          RAND_TEMP(0)                := TEMP;
        END IF;
      END IF;
    END IF;
    RANDOM_NUM <= RAND_TEMP;
  END PROCESS;
END ARCHITECTURE;