48 set device xc4vlx25ff668-10
49 set projName ADDR_FIFO
51 set projDir [
file dirname [
info script]]
52 create_project $projName $projDir/results/$projName -part $device -force
53 set_property design_mode RTL [current_fileset -srcset]
54 set top_module ADDR_FIFO_exdes
55 add_files -norecurse {../../example_design/ADDR_FIFO_exdes.vhd}
56 add_files -norecurse {./ADDR_FIFO.ngc}
57 import_files -fileset [get_filesets constrs_1] -force -norecurse {../../example_design/ADDR_FIFO_exdes.xdc}
58 set_property top ADDR_FIFO_exdes [get_property srcset [current_run]]
63 write_sdf -rename_top_module ADDR_FIFO_exdes -file routed.sdf
64 write_verilog -nolib -mode timesim -sdf_anno false -rename_top_module ADDR_FIFO_exdes routed.v
65 report_timing -nworst 30 -path_type full -file routed.twr
66 report_drc -file report.drc
67 write_bitstream -bitgen_options {-g UnconstrainedPins:Allow}