otsdaq_prepmodernization  v2_05_02_indev
fadc_params_package.vhd
1 -------------------------------------------------------------------------------
2 --
3 -- Title : fadc_params_package
4 -- Design : CAPTAN
5 -- Author : rrivera
6 -- Company : CD_CEPA_ESE
7 --
8 -------------------------------------------------------------------------------
9 --
10 -- File : fadc_params_package.vhd
11 -- Generated : Mon Jun 9 15:12:08 2008
12 -- From : interface description file
13 -- By : Itf2Vhdl ver. 1.20
14 --
15 -------------------------------------------------------------------------------
16 --
17 -- Description :
18 --
19 -------------------------------------------------------------------------------
20 --{{ Section below this comment is automatically maintained
21 -- and may be overwritten
22 --{entity {fadc_params_package} architecture {fadc_params_package}}
23 
24 library IEEE;
25 use IEEE.STD_LOGIC_1164.all;
26 use IEEE.STD_LOGIC_ARITH.all;
27 use IEEE.STD_LOGIC_UNSIGNED.all;
28 package fadc_params_package is
29 
30  constant MEM_ADDR_SIZE: integer := 10; -- number of bits in memory address (RAM must use entire address range)
31  constant BURST_WE_DELAY: integer := 15; -- number of master clocks to delay betweenburst writes
32 
33 end fadc_params_package;
34 package body _fadc_params_package is
35 -- Functions and procedures
36 end fadc_params_package;
37